Hi, I’m
Ratnala Venkata Prasad
Bengaluru
Summary
Aspiring to contribute to pioneering advancements in Analog IC Design by applying my inventive mindset and technical acumen to foster sustained organizational growth in response to ever-evolving global technological landscapes.
Overview
14
years of professional experience
Work History
Incise Infotech Limited
Analog Circuit Design Engineer
09.2024 - Current
Job overview
- Currently working with Incise Infotech Limited as Analog Circuit Designer
Global Institute of Integrated Circuit Technology (GIICT)
Analog IC Design Trainee
09.2023 - 05.2024
Job overview
- Designed and verified analog circuits using UMC 28nm technology node.
- Developed Capless LDOs, Bandgap References (BGR), two-stage OTAs, and multi-OTA architectures.
- Strong proficiency in analog bias circuits (OTA, BGR, LDO, RC-circuits).
- Expertise in stability analysis, Bode plots, pole splitting, dominant pole theory, Miller compensation.
- Conducted PVT corner and Monte Carlo simulations using Cadence design tools.
- Applied advanced circuit analysis techniques for robust and high-performance designs. Passionate about delivering innovative analog/mixed-signal IC solutions for emerging technologies.
- 9 months
SVBC (Sri Venkateswara Bhakti Channel)
Technical intern
10.2011 - 04.2012
Job overview
- In this organisation, I gained extensive hands-on experience by working in various departments encompassing program recording, and live telecast.
- This role provided me with valuable field experience, allowing me to apply the theoretical knowledge I acquired in my classes.
- 6 months
Education
VIT University, Vellore
M.Tech from VLSI Design
05.2024
University Overview
GPA: 7.89/10
RGMCET, Nandyal
B.Tech from Electronics and Communication Engineering
05.2015
University Overview
GPA: 80.56%
S.V.GOVT.Polytechnic
DIPLOMA from Electronics and Communication Engineering
05.2012
University Overview
GPA: 93.19%
A.P.Residential School, Mukkavaripalli
SSC from A.P.State Board
05.2009
University Overview
GPA: 91.66%
Skills
Hardware Description Languages: Verilog HDL
undefinedTimeline
Analog Circuit Design Engineer
Incise Infotech Limited
09.2024 - Current
Analog IC Design Trainee
Global Institute of Integrated Circuit Technology (GIICT)
09.2023 - 05.2024
Technical intern
SVBC (Sri Venkateswara Bhakti Channel)
10.2011 - 04.2012
VIT University, Vellore
M.Tech from VLSI Design
RGMCET, Nandyal
B.Tech from Electronics and Communication Engineering
S.V.GOVT.Polytechnic
DIPLOMA from Electronics and Communication Engineering
A.P.Residential School, Mukkavaripalli
SSC from A.P.State Board
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