Raviram Jayaraman

Accomplished Physical Design Engineer with 10+ years of experience in executing complex RTL2GDSII flows and achieving full sign-off closure across multiple advanced process nodes and low power MPP designs. Skilled in scripting with Shell, TCL and Python for flow automation and efficiency improvements. Demonstrated ability to lead design efforts in high-performance SoCs, with a consistent record of successful tape-outs and cross-functional collaboration.

3nm - PCIe7 (~15M)

• Lead PCIe7 top and block RTL2GDSII implementation and Sign-Off to closure using FPM flow and achieve improved PPA.
• Perform design planning, provide floorplan instruction to partition owners, provide design and constraint feedbacks to design team.
• Provide technical guidance / assistance to team members, create methodologies and scripts to enhance execution and analysis quality.
• Create standardized flow and methodologies which can be used by customers of PCIe7 and to help them achieve best PPA metrics.

3nm - UCIE (~8M) ; PCIe6 (~8M)

• Provide PPA improvement techniques to implementation team, guide them with execution methods and implementation guidance to help them achieve their PPA targets.
• Develop cutting edge FPM flow methodologies for implementation and Sign-Off and deliver to customer.

3nm - ARM core (Target FMAX: 3.4GHz)

• Provide technical assistance to balance the skew between top and block. Help create CTS strategies to achieve latency and skew targets.
• Scripts to identify critical paths, generate ECOs to fix timing and achieve FMAX targets.

5nm - PCIe5

• Develop TCM Constraint verification, promotion, demotion and equivalence flow. Validate the flow, work with R&D team to develop / enhance the flow.

3nm - PCIe6

• Using PCIe6 design as base develop technology packages for TCM, DRC, LVS, PRIMETIME, PRIME CLOSURE, STARRC, VCLP and RV checks.
• Develop the flow, implement the flows, test and validate and deploy to customer. Provide support to customers.
• Port the RM flow created into FPM wrapper and perform regression test.

10nm - Server GPU (~1.2M)

• Critical timing interface paths closure using custom methodologies, clock pre-route planning, custom clock building, register level planning without performance degradation.
• Dynamic interface constraint creation helped to reduce interface timing closure turn around time.
• Clock feed-throughs were planned efficiently to take care of clock insertion across all the block in design.

10nm - Server GPU (~1.7M)

• Multi die interface partition with 2GHz main clock. Special clock strategies to achieve clock skew targets as less as 50ps.
• Placement of macros, especially the placement of PPLs and custom routing of clock routes were planned meticulously to achieve optimal results.
• Clocks exit ports to other blocks were pre-routed with NDRs and custom routes to matches latency across multiple clock exit points.
• Special techniques like MPCTS / MSCTS and CTMESH were achieved by using in-house clock builder methodologies.
• Efficient planning of voltage areas and pg regions to reduce congestion and to better handle cross clock paths. VCLP checks were performed and design feedbacks were provided promptly to reduce turn around time.

28nm - Qualcomm (Ferrolite_cate6, Stingray and NapaliQ)

• RDL and analog routing of IPs and bumps. Review and validate the routing with the IP owner.
• Perform bump to bump, clamp to bump and clamp to clamp resistance verification and performed fixes based on the reports to achieve robust RDL routing network.