RAVI TEJA VELICHETI

• Implemented Design Changes in Serialiser in Transmitter (Intel 18A technology)
• Working on a POC related to Auto place and route in virtuoso studio
• Guiding juniors and reviewing their modules

• Scratch design of High speed RX having input bandwidth of 32GHz and each V2D in RX runs at 8GHz which is new architecture( 28nm TSMC process)
• Designed PLL ( TSMC 16nm Technology) generates 18GHz clocks provides reference differential clocks to Receiver, Transmitter and some single ended clocks to Digital.
• Scratch design of ADC_INTEGRATOR Block works at 6GHz frequency, which gives differential input to ADC (16nm TSMC process)
• Handled Full ADC Hierarchy during tape-out time and implemented design changes and did physical verification (16nm TSMC process)
• Scratch design of CLK_BUFFER and CLK_D2S blocks which are at 3GHz frequency and providing main clocks to ADC’s on a chip (28nm TSMC process)
• Scratch design of Full Custom Memory works at 2GHz (28nm TSMC process)
• Scratch design of Reference Voltage and current block, which includes design of BANDGAP, which procures reference voltage and fed to V2I block which gives different reference voltages and feeding to I-Refgen which gives different Currents for full chip (16nm TSMC process)
• TX- Main Clock path, which has differential clocks running at 16GHz. Placement and RC optimization (16nm TSMC process)
• High precision ADC’s sub-blocks (TI 65nm process)
• Scratch design of Input Buffer block, which receives high frequency Analog Input signals to ADC, RC- parasitic are more important to meet the design specifications.
• Scratch Design of Voltage Reference Ladder block, which produces reference voltage to the Flash Comparators.
• Scratch design of Delay Locked Loop block, which produces delayed clocks used for SAR Comparator and produces other reference clocks which are used internally in ADC
• Scratch design of Data Output Buffer block, which send the highly sensitive ADC Output Data outside the chip
• Scratch Design of Local LDO, which produces clean supply to the ADC comparators and sub-blocks.

· GLOBAL -ALIGN & Tech-Readiness-Work of TSMC-5nm

· Working from Scratch, Criticality from Floor Plan Prospective is to exactly align in SAR-Block so the DATA and Valid signals are planned to align exactly to avoid routing complexity.

· Two clock signals which are driving the Flops need to be symmetric throughout the block.

· Lane-Bias is DC block targeted to provide accurate DC currents to other blocks(customers) in lane (both TX and RX blocks) (10nm Finfet)

· Worked from Scratch Design, Criticality from Floor Plan Prospective include Planning of Array of P-devices (Ptop) and N-devices (Ntop) to meet density requirements.

· As this block need to sit in RX it should meet top level requirements majorly including POWER planning which draws nearly 6-7mA.

· Planning of Stability MIM-CAP is one of the Major Challenge.

· LVDS – RECEIVER (14nm FinFet)

· LVDS Receiver works for both 3.3v and 1.8v and works at frequency of

· 300MHz, which meets the Industrial LVDS standards.

· Worked from Scratch Design, Complete floor plan of the Macro, including planning of floor plan for symmetric devices (i.e PAD Connections of Differential Signals)

· Worked to satisfy the current ratings of the differential signals.

· Complete understand and worked on POWER Mesh at Macro Level and make the Macro compatible with GPIO Ring.

· LVDS-TRANSMITTER (22 FDSOI)

· LVDS Transmitter works for both 1.8v and works at frequency of 1GHz, which meets the Industrial LVDS standards.

· Worked from Scratch Design, Complete floor plan of the Macro, including planning of floor plan for symmetric devices (i.e PAD Connections of Differential Signals)

· Worked effectively to route the Clock signals with same (RC-delays) to trigger the Main Driving Block

· GPIO – GENERAL PURPOSE I/O (14nm FINFET)

· General Purpose I/O works at 3.3v

· Understood and worked on Power Mesh of GPIO Ring

· Chip Level understanding of the I/O circuit and Verification at Chip level.

· Worked on basic ESD blocks (pre-build templates) including RC-Clamps ad Back-to- Back Diode network.