REDDI DEVADEEP

As a VLSI enthusiast, I completed a 6-month internship as a NAND Product engineer in Micron Technology, gaining valuable experience in post-silicon validation and HSPICE simulations. Along with Post Silicon my expertise includes Verilog, RTL design as well. I have a solid understanding in digital IC, analog IC, and physical design. I am enthusiastic about pursuing hardware roles.

ASYNCHRONOUS FIFO - VERILOG

1. Designed and implemented an Asynchronous FIFO module, incorporating read and write pointers, data storage, and control logic to optimize data buffering efficiency.

2. Addressed Clock Domain Crossing Challenges by synchronizing across different clock domain signals ensuring proper data integrity and minimum metastability.

3. Conducted simulation using Xilinx Vivado and performed Functional verification to FIFO memory by writing testBenches. 

6T SRAM CELL - CADENCE 

1. Designed a 6T SRAM cell using Cadence.

2. Analyzed cell ratio and pull ratio during read and write operations .

3. Evaluated Static Noise Margin to ensure the robustness and reliability of SRAM cell . 

LOW POWER BANDGAP REFERENCE CIRCUIT - CADENCE 

1. Designed a BGR circuit that provides precise constant reference voltage which doesn't vary across temperature and supply variations.

2. Attained high PSRR in high frequency as well as low frequency region.

3. Maintained stable reference output voltage with a minute variation of 150 uV at different temperatures from 0 to 100C.