Rehan Raju Nagula

Post Silicon Validation Engineer with 2 years, 10 months of expertise in DDR testing and functional verification on cutting-edge 4nm Android chipsets. Proficient in C and Python, leveraging strong analytical skills to enhance system-level testing efficiency.

Adept at utilizing advanced testers and handling tools, ensuring high-quality outcomes in fast-paced environments and

validated the VDK simulator IP using embedded c in pre-silicon environment and worked on EVM boards using CCS and worked on FPGA boards as well.

• Developed test cases for the UART in embedded C for testing the simulator for pre-silicon activities.
• Developed BCDMA,PKTDMA test cases
• Developed the SPI Test cases.
• Debugged the failure test cases and cross communicated with design and software teams for patches.
• Debugged using the test cases using VDK simulator by data watch and software memory.
• Code freeze using the bitbucket and released to customer.
• Debugged the boot code for auto reboot to default boot.
• Worked on validation of old test cases using CCS on EVM boards
• Worked on FPGA boards for programming the particular IP and developing and validation of IP

• Good understanding of Android architecture and boot process
• Validated the software: UEFI, HLOS, and SVE content to ensure it meets the requirements
• Bring up the bench setup and handlers, like the Chroma handler and Teradyne Titan
• Validation of the test program, which contains UEFI, HLOS, and SVE stress tests on handlers like the Chroma handler and Teradyne Titan
• Communicated with cross-functional teams like SW teams to come up with a solution in case of failure and checked the SW/HW interactions under various conditions
• Debugged the production failures to come up with a solution on SOC IP and boards.
• Worked on SLT Test time reduction and test time optimisation activities
• Analyzed and summarized the production failure devices data by checking the consistency of failures, debugging them to prevent the same failure from recurring in the future, and calculating the DPPM,
• Raising JIRA tickets and monitoring the production data by O+
• RMA analysis.
• Flashed the software using the JTAG and debugged using the JTAG and Trace32 software

• Silicon is bring up at the wafer level, and it is checked whether the die responds, and we continue to check at the FT package
• Worked with cross-functional teams to troubleshoot issues
• Worked on functional verification, Vmin Analysis, PVT characterisation, and yield improvement
• ATE SOC program development
• Test Time Reduction activities for Test Time Optimization
• Used version control tools like Git
• Test program packaging and release
• ATE vs. System Correlation
• HTOL analysis
• JIRA and production data handling tools, like O+,

• PVT characterisation on 1000+ devices and summarised them.
• Modified the python script to add the Data to n number of times to the pattern which reduced the manual time by 70%
• Bringup the chroma handler in constrained timelines for validation of devices using the TP
• Debugged the SLT Devices in stipulated timeline for smooth execution of project
• Developed a script for adding unique id for logs