Revanth Reddy Nayakanti

Role & Challenges

• worked with DTECH team on power grid customization
• Customized power grid based on PDN review feedback to meet IR drop targets and ensure robust power integrity across critical design regions.
• worked with PPA Team on regressions Executed automated PPA regression runs across design milestones, identifying timing, power, and area deviations; enabled early issue detection and contributed to 15% improvement in overall design convergence.

• Worked on the complete design, verification, and implementation of a full chip from RTL to GDSII. Responsibilities included IO placement, floor planning,power planing, placement, clock tree synthesis, routing, timing closure, and Formality.
• Developed and optimized the design flow for Place and Route (PNR), StarRC, PrimeTime (PT), Design Rule Check (DRC), and Layout Versus Schematic (LVS) Taking Reference Flows from Solvnet.
• Contributed to the chip design for tape-out, ensuring adherence to industry standards while implementing custom flows. Challenges Creating Custom Flows for ICC2 , FM , DRC etc using reference flow scripts from Solvnet Congestion Critical chip made implemented methods to resolve it Floorplan changes to achieve Timing and congestion Creating custom power rings around digital (AON and ONO ) domains and also around the analog for the LVL supply IO placement and there tapping to core Area recovery method to fix hold violtions
• Responsible for the closure of the block right from netlist to GDSII implementation
• Timing closure Challenges
• Floor plan was a major challenge, in terms of timing and congestion.
• Done Multiple Floor plan iterations to balance between Routing and Timing issues.
• Dynamic IR drop was critical which required usage of a lot of decap cells for reduction
• Had used clock shielding techniques for reduction of noise and Signal Integrity (SI) issues
• Responsible for the closure of the block right from netlist to GDSII implementation
• Timing closure Challenges DRC cleaning was the major issue I have seen Fixing Congestion at the rectilinear cut Fixing shorts over the Macros Floorplan changes

Worked on two blocks from fixing the Floorplan and PNR by cleaning the timing and DRC

clkx3y2_t (AON+PG)

o Technology: 5nm

o Macro Count: 3 (one system PLL)

o Standard Cell Count: 78,007

o Area: 52,500mm²

o Supply: 1.1V, 0.9V

o Clocks: 5

o Metal Layers: 16

mp1_t (HYBRID)

o Technology: 5nm

o Macro Count: 23

o Standard Cell Count: 500,887

o Area: 82,400mm²

o Supply: 0.65V, 0.6V

o Clocks: 6

o Metal Layers: 16