Richa Agrawal
Senior Lead Engineer, Qualcomm Inc
Bengaluru,KA
Summary
- Richa is a highly driven individual with excellent analytical, problem-solving and communication skills in dealing with multiple stakeholders across geos.
- Expertise over TCL/PERL/Python/Git for Design Flow Automation and debug capabilities.
- Expertise over Basic Device Physics, Custom Analog Sign-off flows involving the Electromigration, Self-Heating, IRdrop Thermal checks over design/Power Grids with industry Standard tools like Totem, Redhawk, Voltus-Fi.
- Expertise over Analog/Digital/Mixed Signal PEX-LVS flows Methodology/Support/Enablement.
- Lead a nuclear team of Soc Design Engineers, mentor and guide them in implementation of RV & Extraction processes.
- Working on Industry standard high frequency parasitic RC analysis tools like HFD, EMX, PeakView. Great presentation skills and has showcased multiple solutions across global forums.
Overview
8
8
years of professional experience
Work History
SENIOR LEAD ENGINEER
Qualcomm Incorporated
Bengaluru
06.2024 - Current
- Working with two junior engineers to setup VARIOUS PEX flows for SOC for instance, setup VMF flow for signoff extraction and also inside FC/innovus, identified multiple bugs related to boundry model in Starrc and Quantus Extraction.
2. Worked extensively in 3DIC and 2.5D IC flows for PEX and PDN. In developing the hybrid flow to support interface extraction and STA flows. In developing interposer extraction for 2.5D IC and its impact on SIGNAL/ power EM FLOWS.
3. Worked to set up IP modelling or PGV flows, for std cells, macro, switches,overlay etc. and resolve bugs within Voltus for PGV vs FSDB/SPF mismtach.
4. Worked to rootcause signal EM optimism coming due to thermal profile of design, and extraction settings for EMIR SPEF.
5. Worked to support project setup, flow, and tool validation for almost 9 to 10 projects per year for extraction and EMIR.
6. Worked to resolve flow bugs in RTL, and zero-delay flows in vectorless EMIR analysis.
STAFF CAD ENGINEER
Marvell Technology Pvt Ltd
Bengaluru
04.2023 - 06.2024
- Worked on setting up the Digital PEX extraction flow in a recently created CAD team, releasing for industry-standard engines like QRC and StarRC for cutting-edge nodes, such as 2/3/5nm TSMC, Samsung, and Intel like QRC, StarRC for cutting edge nodes, like 2/3/5nm TSMC/Samsung/Intel.
- I worked in parallel on exploring industry-standard high-frequency parasitic RLC engines, such as Peakview, EMX, and HFD. Establishment of benchmarking and comparison between these for complex, custom analog designs.
SoC DESIGN ENGINEER
Intel Corporation
Bengaluru
06.2018 - 04.2023
- Enabled extraction methodology for Custom Analog CBB Timing flows, Post Layout Simulation Flows, Sign-Off Flows.
- Was the sole person responsible for debugging Custom Analog PEX and PEX-LVS Issues from India for multiple BUS.
- Explored and performed accuracy evaluation of Cadence Voltus SD Sign-Off tool for CBB designs, involving handshaking with Voltus-FI, Primetime Custom Flow Tools.
- Worked on Enabling Accurate Extraction Methodology for Voltus-Fi based Custom RV solutions using StarRC, QRC engines.
- Designed Efficient EMIR Solutions for Big Custom Analog CBB designs at lower process nodes using Cadence Voltus-Fi.
- Implemented dynamic and static Sign-Off collateral handshake between Custom Analog to Digital RV Flows.
- Established RV Flow to calculate RV compliant max Cap and generate .LIB characterization files of a High-Speed Custom Standard Cells.
- Improved efficiency of Vectorless Voltus Sign-Off flows for complex designs where spectre/hspice simulations have runtime roadblocks for Huge Custom Analog designs.
- Worked on designing and optimizing EM/IR of a Robust Power Grid on a 22nm design using Redhawk GPS tool to meet the specified design constraints of the IP where it was instantiated.
SOC DESIGN INTERN
Intel Corporation
Bengaluru
06.2017 - 05.2018
- Master's Thesis on designing and optimizing EM, IR of a Robust Power Delivery Network through Redhawk GPS solution for a 22nm process (Digital Reliability Verification).
- Worked on ASIC Design Flow & Tool Flow methodology with Industry standard custom Parasitic Layout Extraction and Sign-Off tools like StarRC, Totem Reliability Integrity Solutions.
- Extensively involved in 3D IC Chip Package Modelling for 22 nm IceLake Servers.
Education
Master of Engineering - Microelectronics
NIT
Warangal, TG, India06.2018
Bachelor of Engineering - Electronics & Communication
RGTU
Jabalpur, MP, India08.2014
Skills
- Effective communication
- Adaptability & Cooperation
- Negotiation & Persuasion
- Analytical & Problem Solving
- Teamwork and Collaboration
- Presentation
EXPERTISE
- VoltusFi : Advanced
- ICV-StarRC : Expert
- TCL/Perl/Python : Advanced
- Virtuoso & Spectre : Intermediate
- Voltus EMIR : Intermediate
- Calibre-QRC : Expert
AWARDS
- DRA & DIA awards at Intel for excellent work in RV & PEX flow efficiency improvements for PCIe/PLL/MIPI/DP etc analog IPs.
- Received Best Presentation Award in CDN Live India 2022 for paper on 'Efficient EMIR Solutions using Voltus-Fi for Lower Process Nodes'.
- Received Acceptance for Poster Presentation in Global DAC conference for paper on Voltus 'EMIR Signoff Methodology for Large Size Mixed Signal Custom Blocks in High Speed IOs'.
- Received Merit Scholarship from the Vice Chancellor of RGTU in UG.
REFERENCES
- Ayan Roy Chowdhury, Principal Engineer, Intel, ayan.r.chowdhury@intel.com
- Luis Abreu, SoC Design Engineer, Intel, luis.abreu@intel.com
- Sainarayanan KS, Director CAD, Marvell, skaratholuvu@marvell.com
LANGUAGES
Spanish : Intermediate
English & Hindi : fluent
Timeline
SENIOR LEAD ENGINEER
Qualcomm Incorporated
06.2024 - Current
STAFF CAD ENGINEER
Marvell Technology Pvt Ltd
04.2023 - 06.2024
SoC DESIGN ENGINEER
Intel Corporation
06.2018 - 04.2023
SOC DESIGN INTERN
Intel Corporation
06.2017 - 05.2018
Master of Engineering - Microelectronics
NIT
Bachelor of Engineering - Electronics & Communication
RGTU