RINKU SINGH
Summary
Synopsis 10+ years of experience as Design and Verification Engineer in EDA semiconductor industry. Looking for an opportunity in a challenging role with immense learning and growth.
Overview
10
10
years of professional experience
4
4
years of post-secondary education
Work History
Cadence
01.2017 - Current
- Working as a product validation engineer, in simulator validation team
- Worked on multi core simulation feature validations
- Working on low power simulation, new feature validation in UPF and CPF
- Helps AE’s Debugging customer big Low Power designs
- Cross tools feature testing (Testing in collaboration with other teams)
Agnisys Pvt. Ltd
07.2012 - 12.2016
- IDesignSpec(An IP design tool of AGNISYS):
- IDS is a register/sequence design and management tool which enables Architect/System Designer to capture design specifications in a word/excel document and generate all possible outputs like Verilog, VHDL, UVM etc
- Development of RTL’s Verilog, VHDL, SV (Synthesizable), SYSTEMC (Synthesizable)
- Special Registers such as shadow, shared, aliased, lockable, trigger buffer registers
- Generation of UVM Sequences from Sequence information captured in IDS
- Verification of RTL outputs through directed test bench in SV, and created a verification environment in UVM
- Design and verification IDS RTL slave for the following ARM standard buses
- Used MENTOR’s VIP and internal tool name ARV(Automatic register verification) tool to verify the design
- AMBA-AXI4LITE
- AMBA-AHB
- AMBA-AHB3LITE
- AMBA-APB
- Writing, directed test bench for Testing the RTL’s VERILOG, VHDL, and SV
- Wrote Perl/TCL scripts for the setup Regression environment
- Support customers on their issues related to the RTL’s thru email or remote session
- ARV(Automatic Register Verification)(Agnisys tool):
- ARV is a complete Register Verification solution using complementary methodologies, simulation and formal
- ARV helps to auto generate UVM testbench, bus agents, monitors, drivers, adaptors, predictors, sequencers and sequences, giving users the means to complete the verification right the first time
- The aim of this product is to do 100% automatic generation and verification of the whole of the address map
- I am leading the product my responsibilities include –
- Research methods on how registers can be fully functionally verified
- Create UVM models of normal registers as well as a lot of quirky registers like shadow, aliased, lockable registers, modal, ro-wo pair etc
- Create UVM model to automatically verify transaction from multiple buses as well as the Hardware side interface which includes creation of agents of various standard buses like AXI, APB, AHB, AVALON, Proprietary etc
- Create Bus agents for each supported bus namely AMBA AHB, AMBA APB, AMBA AXI4Lite, AVALON, AMBA3AHBlite, Proprietary Bus
- Create Sequence Library containing all sequences for each sw access type and special cases of locked, shadow, aliased etc
- Registers
- Creation of the UVM based environment and tests which integrate all the components
- Software Implementation to get all of these components automatically generated
- Verifying the user register and memory through HDL Path
- ISequenceSpec(A sequence generation tool of AGNISYS):
- ISS is a sequence generation tool which enables HW and SW verification engineer to capture sequence flow in specifications using word/excel
- And generate all possible outputs like Validation, Verification, and Firmware etc
- IVerifySpec(A verification management tool of AGNISYS):
- IVS is a verification management tool which helps verification engineers to manage the verification plan and result
- It helps to debug the issue easily, and representation of the results.
Education
VLSI Design -
DKOP Labs
B.TECH - Electronics and Communications Engineering
Gautam Buddh Technical University
01.2007 - 01.2011
Skills
ToolsQuesta Sim, NC-Sim, VCS, Synplify proHDL’s : Verilog, VHDL, SV SystemCHVL’s : System Verilog, UVMScripting Language : Perl, Tcl, ShellPrograming Language : C, CSimulation technology : Low Power ( UPF and CPF)Version control : Git-Hub, Clear Case, perforce
Timeline
Cadence
01.2017 - Current
Agnisys Pvt. Ltd
07.2012 - 12.2016
B.TECH - Electronics and Communications Engineering
Gautam Buddh Technical University
01.2007 - 01.2011
VLSI Design -
DKOP Labs