Summary
Overview
Work History
Education
Skills
Certification
Projects Undertakes
Accomplishments
Timeline
Generic

RITIBH SINGH

Bangalore

Summary

Dedicated and highly motivated Hardware Engineer with a solid foundation in Verilog coding and FPGA design flow seeking position in Design and Verification roles. Possess a strong enthusiasm for learning and growing in the field of VLSI, particularly in the frontend domain. Knowledge in industry-standard EDA tools like Synopsys, Cadence to contribute meaningfully to high-performance projects. Proven ability to identify and resolve hardware-related issues through systematic troubleshooting and debugging processes. Eager to leverage existing skills, coupled with a commitment to ongoing learning, to make meaningful contributions to innovative hardware engineering projects. Proven team player with a solid foundation in cross-functional collaboration and a track record of delivering high-quality results

Overview

1
1
year of professional experience
1
1
Certification

Work History

IP Logic Design Engineer Intern-IPSE Team

Intel
07.2023 - Current
  • Job Role: As Part of the IPSE Design team at the FPGA group of Intel, our job is to deliver IPs to customer as part of Quartus Prime's IP catalog.
  • Hands-On experience: Working on Transceiver IP, understanding PHY Architecture, hands-on experience on the TCL framework to validate IP parameters on the GUI and getting familiar with the FPGA flow.
  • Simulation and Synthesis: Running ED simulations and Quartus Flow for Compilation, Synthesis, Place and Route, Timing Analysis
  • Debugging and Analysis: Working on DPHY Working with the team to clear out issues related to IP and running regressions to keep track of the test cases and monitor IP Health.
  • IP Quality Checks: Improving IP quality and running IP checks for Spyglass CDC, LINT, QMR checks, Regression checks, Quartus checks, SCTH checks.

Education

M.Tech - VLSI Design

Vellore Institute of Technology
Vellore
05.2024

B.Tech - Electrical And Electronics Engineering

KIET Group of Institutions, AKTU
Ghaziabad
08.2020

CBSE, Class 12 - Science

Lucknow Public School
Lucknow
04.2015

Class 10, CBSE - Science

Lucknow Public School
Lucknow
04.2013

Skills

  • Scripting: TCL, BASH
  • Hardware Description Language: Verilog HDL, System Verilog for Design and Verification
  • EDA Tools: Intel Quartus, Xilinx Vivado, Synopsys VCS, Cadence Virtuoso
  • Areas of Experience: Direct-PHY, RTL Design, Logic Design, Verilog and System Verilog coding, Basics of Formal Verification, Clock Domain Crossing Analysis, Timing Analysis, Spyglass CDC, LINT, FPGA Architecture, ASIC Flow

Certification

  • System verilog for Verification - Udemy
  • Bash scripting - Udemy
  • Verilog for an FPGA Engineer using xilinx vivado - Udemy
  • Intel FPGA'S - Intel
  • TCL Scripting - Synopsys
  • Formal Verification Basics - Degreed

Projects Undertakes

Implementation of 6T SRAM Cell 

  • Design of 6T SRAM cell in Cadence Virtuoso in 180nm technology.
  • Transistor sizing of NMOS and PMOS transistors to achieve Hold , Read and write operations.
  • Obtaining the characteristics of word line and bit line

Design of Asynchronous FIFO using Verilog HDL and its RTL TO GDS 

  • Design of Asynchronous FIFO in verilog HDL and its functional verification using testbench
  • Performing Logical, Physical and Power synthesis
  • Generating timing netlist for Timing Analysis
  • Tools implemented: Prime-Time, icc2 Compiler

Accomplishments

  • Intel Recognition Award : Awarded by Project Manager, PSG Group
  • GATE Qualification : Electrical and Electronics Engineering in 2021, 2022.

Timeline

IP Logic Design Engineer Intern-IPSE Team

Intel
07.2023 - Current

M.Tech - VLSI Design

Vellore Institute of Technology

B.Tech - Electrical And Electronics Engineering

KIET Group of Institutions, AKTU

CBSE, Class 12 - Science

Lucknow Public School

Class 10, CBSE - Science

Lucknow Public School

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