Ritu Mishra
Design Verification Engineer
New Delhi,DL
Summary
Dynamic R&D Engineer with proven expertise at Synopsys in design verification and validation. Recognized for resolving critical bugs and enhancing VIP performance through effective debugging and regression maintenance. Proficient in VCS and Verdi tools, with strong customer issue resolution skills, driving successful product releases and ensuring high-quality outcomes. Results-driven R&D Engineer excelling in design verification and validation with strong debugging expertise. Proven ability in managing I2C and I3C VIP protocols, contributing to successful product releases.
Overview
3
3
years of professional experience
Work History
R&D Engineer (Full-Time)
Synopsys
08.2023 - Current
- Led test case creation, regression maintenance, and debugging across multiple verification environments.
- Executed protocol-level verification for I2C and I3C VIPs utilizing VCS and Verdi tools.
- Managed complete release cycle for approximately 80 Verification IP products, ensuring quality and functionality.
- Conducted multi-stage product validation using various EDA tools to enhance performance of VIP products.
- Collaborated with customers to resolve license issues and debug setup problems for uninterrupted usage.
- Identified and resolved critical bugs affecting multiple product lines, earning recognition from engineering leadership.
- Utilized AI tools VScode and cursor.ai to achieve accurate results during testing.
Verification Engineering Intern
Synopsys
07.2022 - 07.2023
- Supported testcase development and regression maintenance activities for protocol-based verification.
- Assisted in debugging simulation failures using VCS and Verdi.
- Participated in validation tasks contributing to VIP release readiness.
- Worked closely with engineering teams to analyze failures and improve verification coverage.
Education
Master of Science - Electronics
University of Delhi
Department Of Electronics South Campus07-2022
B.Sc. - Instrumentation
University of Delhi
Shaheed Rajguru College Of Applied Sciences 07-2019
Class XII - PCMB
CBSE
SKV Vikas Puri New Delhi03-2015
Class X -
CBSE
SKV Mohan Garden New Delhi 03-2013
Skills
- Design verification and validation
- Testcase development
- Regression maintenance
- Debugging expertise
- I2C and I3C protocols
- UVM methodology
- Synopsys VCS proficiency
- Verdi tool usage
- C programming
- Perl scripting skills
- Linux Command-line expertise
- LSF farm knowledge
- VIP release cycle management
- VIP Licensing support services
- Customer issue resolution
Additional Information
- Strong analytical and debugging skills., Open to opportunities in ASIC/SoC Verification, Verification IP Development, Functional Validation, and Protocol Verification.
Achievements And Recognition
- Recognized for fixing critical verification bug impacting high-priority deliverables.
- Awarded for resolving major license-related customer issues and improving product usability.
- 4th Rank Holder in M.Sc. Electronics Entrance Examination conducted by NTA.
Core Technical Skills
Design Verification, Testcase Development, Regression Maintenance, Debugging, I2C, I3C, UVM, Synopsys VCS, Verdi, C, Perl Scripting, Strong Linux command-line expertise, LSF farm, VIP Release Cycle Management, Validation, Licensing Support, Customer Issue Resolution
Timeline
R&D Engineer (Full-Time)
Synopsys
08.2023 - Current
Verification Engineering Intern
Synopsys
07.2022 - 07.2023
Master of Science - Electronics
University of Delhi
B.Sc. - Instrumentation
University of Delhi
Class XII - PCMB
CBSE
Class X -
CBSE