L1 UL/DL Procedure Development (LTE Cat-1)
- Implemented L1 UL/DL procedures for LTE Cat-1 devices with MAC-PHY, MAC-RRC, and MAC-PDCP integration using IPC mechanisms.
- Focused on uplink modules including PRACH, PUCCH PUSCH, SPS, TTI Bundling, and Uplink Power Control in compliance with 3GPP standards.
- Designed FSM-based control framework for interrupt handling and real-time task scheduling, achieving ~5 Mbps UL and ~10 Mbps DL per user while supporting 12,000+ concurrent users.
Reference Module (RM)Development
- Developed frequency tracking, time tracking, and delay spread estimation algorithms, improving PHY synchronization accuracy by ~95%.
- Contributed to overall PHY performance optimization, reducing channel estimation errors by ~20% in varying RF conditions.
L2 Layer Development – 5G NB-IoT
- Developed L2 user-plane MAC, RLC, and PDCP functionalities for a 5G NB-IoT project, achieving 100% protocol feature coverage as per project scope
- Implemented and validated procedures for PRACH, PUSCH, SPS, PHR, PDCCH, and PDSCH channels.
3GPP Standards & Protocol Knowledge
- Strong working knowledge of 3GPP specifications (Release 10–15) across PHY, MAC, RLC, PDCP, and RRC layers and experienced in translating 3GPP requirements into implementation and validation.
L1 FPGA Validation & Field Testing
- Performed lab validation and field testing (FT) for 4G LTE and 5G NB-IoT with BSNL, Jio, Airtel, and VI, achieving 100% end-to-end feature validation.
- Analyzed protocol traces and field logs to debug issues, ensuring system stability and feature compliance.
Low-Power Framework & Recovery Design
- Designed and implemented PHY Master Reset logic to gracefully reset RTL-PHY and recover from system-level failures.
- Enhanced robustness and recovery during critical fault scenarios.
L1 Architecture & Real-Time Systems
- Hands-on experience with L1 architecture, interrupt handling, real-time event scheduling, multi-core and multi-threading.
- Skilled in timing-critical embedded system design and optimization.