Rohit Choubey
Rewa
Summary
I am looking for a VLSI position where I can utilize my skills, abilities, and potential to grow professionally. I am seeking a career that fosters my development and offers opportunities for continuous learning, teamwork, and the expansion of my experience.
Overview
3
3
years of professional experience
Work History
RTL Design and FPGA Engineer
IIITB
Banglore
04.2023 - Current
Currently, I am working as a IIIT Bangalore Research Associate (Project Staff) Engineer.
- Testing of various IPs of 5G NR PDCCH (Physical Uplink Control Channel) chain.
- Writing test benches in Verilog to verify the functionality of the IPs.
- Testing IPs on FPGA boards (Zynq Ultra Scale RFSOC ZCU111)
- Tool used: Xilinx ISE, Xilinx Vivado, Vitis
Internship
Ericsson India PVT LTD
Gurugram
07.2021 - 06.2022
- Design Engineer at Ericsson India Private Limited in the Ericsson Charging Test and Verification domain. My work is to verify the test case and debug faults in the design.
Education
M.Tech - VLSI Design
Thapar Institute of Engineering & Technology
Patiala (Punjab)09-2022
BE - ECE
Rajiv Gandhi Proudyogiki Vishwavidyalaya
Bhopal, MP07-2017
Skills
- HDL: Verilog HDL
- HVL:System Verilog
- TOOLS:Mentor Graphics- Questasim, Cadence Virtuoso (Spectre), Calibre, Mentor graphics (tanner), ICC2, Prime time
- SOFTWARE PACKAGE:Xilinx ISE, Xilinx Vivado, Vitis
- Operating system:Linux, Windows, UNIX
- Protocol Knowledge:APB, PCIE (Basic knowledge
- FPGA Board:Zynq Ultra Scale RFSOC ZCU111
Having good knowledge of VLSI fundamentals, FPGA architecture, CMOS and MOS theory, Digital VLSI Design, ASIC FLOW
M.Tech Project
- Design and Verification of Synchronous and Asynchronous FIFO using Verilog Code.
Description: In this project, write an RTL code for synchronous and asynchronous
FIFO and write a test bench to check the functionality with the help of Viviado.
- Design of a pattern detector using Verilog.
Description:A pattern detector for serial input has been designed using both Moore
and Mealy Finite State Machines (FSMs). The FSM observed a change in the number of of states, requiring the coding of an FSM to detect each pattern until it reaches the final
pattern. To verify the functionality, a test bench was implemented that generated random sequence of 0s and 1s to validate the pattern detection mechanism.
TRANNING & CERTIFICATE
- Maven Silicon Pvt Ltd, Bangalore (RTL Design & Verification) (SEP 2022 to April 2023)
[Digital Design, STA, Verilog, CMOS Design] - PCIe Training from VLSI GURU (September 2023 to till date)
Affiliations
I worked as a teaching assistant for 1.5 years during my M.Tech
Languages
Hindi
First Language
English
Proficient (C2)
C2
DECLARATION
I hereby declare that the above-mentioned information is correct to my knowledge, and I bear the responsibility for the correctness of the above-mentioned particulars.
Rohit Choubey
Timeline
RTL Design and FPGA Engineer
IIITB
04.2023 - Current
Internship
Ericsson India PVT LTD
07.2021 - 06.2022
M.Tech - VLSI Design
Thapar Institute of Engineering & Technology
BE - ECE
Rajiv Gandhi Proudyogiki Vishwavidyalaya
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