Rohith Sai Peddi
Hyderabad
Summary
Accomplished VLSI Physical Design Engineer at Moschip, specializing in advanced node technologies and timing closure techniques. As an expert in floor planning, place, CTS, and detailed routing, I successfully optimized complex designs, ensuring high performance and minimal congestion. A collaborative team contributor, I excel in delivering innovative solutions that meet stringent design requirements.
Overview
4
4
years of professional experience
Work History
VLSI Physical Design Engineer
Moschip
Hyderabad
08.2021 - Current
- Block-7: Technology:3nm Tools: Synopsys Fusion compiler/icc2 , Prime Time, caliber. Instance count: 800k Macros : 0, No. of Clocks : 8 Frequency : 5.07 /2.40 GHz Role : Major part is on Bus planning manually for half cycle paths and full cycle paths, Pre-PNR Checks, floor planning & Placement Optimization, Clock Tree Synthesis, Timing optimization using Clock-opt, SI-aware Routing, RC extraction, STA, Crosstalk analysis. In this block congestion fixing & DRC's are the critical issues.
- Block-6: Technology:3nm Tools: Synopsys Fusion compiler/icc2 , Prime Time, calibre. Instance count: 1.2M Macros : 2, No. of Clocks : 12 Frequency : 2.40 GHz Role : Major part is on Bus planning manually, Pre-PNR Checks, floor planning & Placement Optimization, Clock Tree Synthesis, Timing optimization using Clock-opt, SI-aware Routing, RC extraction, STA, Crosstalk analysis. In this block congestion fixing & DRC's are the critical issues.
- Block-5: Technology:5nm Tools: Synopsys Fusion compiler/icc2 , Prime Time, caliber. Instance count: 2.2M Macros : 152, No. of Clocks : 20 Frequency : 3.389 GHz Role : Pre-PNR Checks, floor planning & Placement Optimization, Clock Tree Synthesis, Timing optimization using Clock-opt, SI-aware Routing, RC extraction, STA, Crosstalk analysis. In this block congestion fixing & timing closure mainly for hold and conflict paths are critical.
- Block-4: Technology : 28nm Tools : Innovus, QRC & Tempus Instance count :812K Macros : 32 No. of Clocks : 10 Frequency : 580MHz Role : Pre-PNR Checks, floor planning & Placement Optimization, Clock Tree Synthesis, Timing optimization using CCOpt, SI-aware Routing, RC extraction, STA, Crosstalk analysis. In this block congestion fixing & timing closure are critical
- Block-3: Technology : TSMC65nm Tools : Innovus, QRC, Tempus Instance count : 323K Hard Macros : 22 Frequency : 220MHz Clocks : 4 Role : Block level Physical design including Floorplan, Power-Planning, Timing Optimization by using various methods like group paths or creating regions, Clock-Tree Synthesis, Detail Routing, Post-Route Optimization, timing closure by writing ECOs from Tempus.
- Block-2: Technology/Layers : TSMC 90nm/6 Metal Layer Tools : Innovus, QRC & Tempus Instance Count : 110K Macros : 6 Clocks : 4 Frequency : 150 MHz Objective : To achieve maximum frequency of operation and minimum global skew of 25ps. Applied the group paths for maximum frequency and to achieve the target skew played with clock tree specification file (changed sink max tran, buf max tran, max & min insertion delays, max fanout), applied NDR rules, dummy loads, H-tree.
- Block-1: Technology : TSMC 130nm Tool : Genus Clocks : 2 Frequency : 200 MHz Role : Writing constraints by understanding the design, lint checks on the RTL and constraints, Synthesizing the netlist to meet the targeted frequency by using various optimization techniques. Dumping all required reports.
Education
M.Tech -
Under Jawaharlal Nehru Technological University
Hyderabad08-2021
Skills
- Place and route
- Layout versus schematic
- Floor planning
- Placement optimization
- Clock tree synthesis
- Timing optimization
- SI-aware routing
- Static timing analysis
- Congestion fixing
- Design rule checking
- Scripting languages
- Team collaboration
- Timing closure techniques
- IR drop analysis
- Synthesis
- Advanced node technologies
Skills Tools
Fusion compiler, Prime Time, Caliber, Genus, Innovus, Tempus, QRC, TCL & csh scripts
Timeline
VLSI Physical Design Engineer
Moschip
08.2021 - Current
M.Tech -
Under Jawaharlal Nehru Technological University
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