Rupali Padhy

• Layout design for integration of electronic components like Analog design templates , MIM capacitors , thin film resistors , Guard rings , Diodes etc to test the quality of PDK
• PV(DRC,LVS,ERC,PERC) and extraction flows to analyze and debug issues in components used using ICV ,Calibre and Cadence PVS , QRC and Star-RC.
• This also includes monitoring and verifying updates in DRM in subsequent process updates and providing solutions for updating tool behavior
• Understanding Fill methodologies and implementation in designs with minimum DR issues. Questioning fill spec and raising new methods for better fill solutions.
• Achieved effective quality assurance for Process Design Kits (PDKs) across diverse technologies, including Intel's 3nm, 7nm, 10nm, 14nm, and 22nm processes.
• Utilized CAD tools such as Cadence Virtuoso and CalibreDrv.
• Created numerous test cases to ensure comprehensive coverage of custom back-end design tools and PDKs
• Trained and developed a robust QA team across Asia pacific geography

SRAM Porting and PV verification

Duration: October 2018 to March 2019- 5 mos.

Description: This is a migration project, in which an SRAM IP is migrated from one dot process to another in 10nm technology.

Responsibilities:

· Update layout based on the new metal stack and DR rule updates.

· Physical Verifications on the IP which includes LVS, DRC checks, antenna fixes and maintaining overall density adhering to RV rules.

· CAD tools used: Cadence Virtuoso, CalibreDrv

DDR 10nm ,14nm Layout Creation - Testchip for Intel 12th and 11th Gen Processors

Duration: June 2018 to September 2018 (4 mos.)

Responsibilities:

• Demonstrated proficiency in creating mixed-signal IO designs, encompassing RX, TX, PLL, and Bandgap bias.
• Generating LEF files, implementing ECO fixes, and verifying layouts.
• Ensuring proper shielding and matching for reference and clock signals.
  Developing intricate layouts for mixed-signal and analog circuits using deep sub-micron CMOS technologies.
• Assessing floorplans and complex circuits collaboratively with circuit designers.
• Coordinating with the circuit design team to strategize and schedule tasks, while managing layout tradeoffs when necessary.
  Interpreting LVS, DRC, and ERC reports to expedite layout completion.
• Surpassing engineering specifications by closely collaborating with the circuit design team spanning different regions.
• Employing advanced CAD tools and mask design expertise to deliver accurate and resilient layouts that fulfill strict criteria for matching performance, area, and power consumption.