S Lavanya
Design Verification Engineer
Chittoor
Summary
RTL Design and Verification engineer with hands-on experience in Verilog, SystemVerilog and UVM-Based verification. Skilled in developing scalable testbenches , debugging complex scenarios , and ensuring functional correctness using assertion-based and coverage-driven methodologies.
Overview
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1
Certifications
Work History
GRADUATE TRAINEE ENGINEER
RV-VLSI Design Center
07.2025 - 01.2026
AMBA APB Slave Verification(UVM) Dec-2025
- Developed UVM testbench to verify read/write operations
- Verified protocol compliance including SETUP and ACCESS phases
- Created testcases for wait states and error responses
AMBA AHB Master Verification(SystemVerilog)
RV-VLSI Design Center
11.2025 - 2025
- Verified burst transactions(INCR, WRAP) and pipeline behavior , Verified corner cases with constrained-random stimulus
- Achieved functional coverage of 72% and improved through targeted tests.
10GE MAC Verification (UVM) Dec 2025 - Jan 2026.
RV-VLSI Design center
07.2025 - 01.2026
- Developed TX/RX agents for packet-level verification ,verified packets using SOP/EOP.
- Developed constrained-random stimulus for varied payload conditions.
Education
Advance Diploma in ASIC Design - RTL Design And Verifcation
RV-VLSI Design Center
01-2026
B.Tech - Electronics and Communication Engineering
Bharath Institute of Higher Education And Research
04.2001 -
Skills
Language: Verilog,SystemVerilog
Verification: UVM , (SystemVerilog Assertions)SVA , Verification plan
Constrained-random verification , functional coverage
Concepts: Digital Electronics ,STA Basics, UVM testbench architecture
Protocols : AMBA (APB,AHB) , Ethernet (10G MAC basic)
Tools : Synopsys VCS , EDA Playground
Others : Debugging , waveform Analysis , linux,OOP Concepts
Certification
RTL Design and Verification
Work Availability
monday
tuesday
wednesday
thursday
friday
saturday
sunday
morning
afternoon
evening
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Languages
English
Upper intermediate (B2)
Telugu
Bilingual or Proficient (C2)
Software
Python
Interests
Singing
Problem solving
Logical thinking
Timeline
AMBA AHB Master Verification(SystemVerilog)
RV-VLSI Design Center
11.2025 - 2025
GRADUATE TRAINEE ENGINEER
RV-VLSI Design Center
07.2025 - 01.2026
10GE MAC Verification (UVM) Dec 2025 - Jan 2026.
RV-VLSI Design center
07.2025 - 01.2026
B.Tech - Electronics and Communication Engineering
Bharath Institute of Higher Education And Research
04.2001 -
Advance Diploma in ASIC Design - RTL Design And Verifcation
RV-VLSI Design Center