Sachin Kanoji
Analog Modelling And Verification
Bangalore
Overview
4
4
years of professional experience
6
6
years of post-secondary education
Work History
Design Engineer ||
Cadence Design System
Bangalore
03.2019 - Current
- Worked on serdes project .
- Developed verification plan . Worked on AMS verification
- Worked on synthesizable coding for emulation
- Worked on checking model vs Schematic(AMSDMV) for correctness of models.
- Coding proficiency is verilog , system verilog for design,understanding of tcl script required for project.
- As AMS engineer worked with different team for debug of issues .
- Tools : Cadence virtuoso, simvision,viva ,vmanager etc are tools used during various project.
Education
Bachelor of Technology - Electronic And Communication
SGGSIE&T
Nanded, Maharashta, India 07.2010 - 05.2014
Master of Technology - VLSI
Vellore Institute of Technology
Vellore,India 07.2016 - 05.2018
Timeline
Design Engineer ||
Cadence Design System
03.2019 - Current
Master of Technology - VLSI
Vellore Institute of Technology
07.2016 - 05.2018
Bachelor of Technology - Electronic And Communication
SGGSIE&T
07.2010 - 05.2014