Sai Kumar Jyothi

Designing a Low Drop-Out Regulator (int18a).

• Designed an NMOS-based LDO for the clock path of the receiver of SerDes IP.
• Performed simulations across all PVTs to achieve the desired PSRR, offset, and stability specifications.

Designing a V2I generator (int18a).

• Designed a V2I generator that generates current for the sub-blocks in the receiver of Serdes IP.
• Performed simulations across all the PVTs to achieve the desired currents, PSRR, offset, and stability specifications.

Top-level power simulations for the receiver of SerDes IP (SF2).

• Debugged the causes of power leakage issues due to various power states in the test chip and fixed them in the product.

• Worked on the V2I generator block in eFlash IP (28 nm node).
• Explored various methods using cadence virtuoso tool to find the capacitor value.