Sai Nitish Chamiraju
ASIC Engineer
Bengaluru
Summary
Collaborative Design Verification Engineer with 10 years of experience leading design, verification of SOC and Subsystem IPs. Considered valuable asset while contributing excellence in cross-functional project leadership to deliver products and solutions on-time. Strong communicator to translate design requirements into actionable plans.
Overview
11
11
years of professional experience
4
4
years of post-secondary education
1
1
Language
Work History
SoC Design Engineer
Intel India Pvt Ltd
Bengaluru
12.2019 - Current
- Collaborated with cross-functional teams to conceptualize and refine product concepts.
- Developed product designs as per SOC specification.
- Working on PPA analysis to enhance product quality.
- Coordinated technical requirements, scheduling and solution development for engineering design and test issues.
- Perform Quality checks as per our standard development flow.
- Debug RTL at IP and SOC level.
Verification Engineer
AMD India Pvt Ltd
Bengaluru
04.2016 - 11.2019
- Worked on verifying Fabric IP.
- Created scenarios at subsystem level to verify Fabric features.
- Bring-up verification environment and test cases to verify features (trace capture Buffer, re-transmit, channel interleaving)
- Participated in code reviews to maintain high-quality standards and identify potential areas for improvement.
- Owned specific hang scenarios and helped in debugging during integration of another IP's
Verification Engineer
EnSilica India Pvt Ltd
Bengaluru
10.2014 - 03.2016
- Build a block level System Verilog environment for Sub-System Verification.
- Analyzing functional coverage and developed directed testcases to cover holes.
- MPHY Verification IP Development: Developed Standard UVM test-bench architecture
- Developed assertions for protocol checks
- Generate sequences to generate Line reset, Register read/writes, speed/gear changes.
- Generate sequences to exercise M-TX and M-RX State machines.
Trainee Verification Engineer
ExpertHDL
Bengaluru
08.2013 - 07.2014
- Design & Verification of UART: Developing the Verification Plan for the UART Protocol
- Micro architecture is developed for Transmitter, Receiver of UART Implemented Reset Synchronizer RTL in Receive path to capture the received Serial Data
- Implementation of Clock domain crossing (CDC) synchronizer RTL in Asynchronous FIFO
- Design and Verification of Round-Robin Arbiter Algorithm: RTL coding done in Verilog and Verification environment built in System Verilog
- Verified features: Generated scenarios to check random requests and grants
- AMBA-APB Verification IP Development: Developed VIP for the AMBA-APB Protocol
- Added new feature of slicing the address range for the slave, based on configurable address width and number of slaves to be selected
- Developed test suite covering all features
- Assertions, checkers and cover groups are implemented.
Education
Bachelors of Technology - Electronics And Communications Engineering
Bharat Institute of Engineering & Technology
07.2009 - 05.2013
Skills
- SystemVerilog
UVM
AMBA Protocols
Cadence Incisive Simulator
Synopsys VCS
Technical documentation drafting
Design concept verification
Additional Information
- Awarded with Silver Medal for obtaining Second Rank at Board Level Achieved Top Rank in the ECE Department at Engineering Level.
- Awarded as the Best Presenter at Fouriers-2K12, a National Event conducted at BIET.
- Efficient in feature extraction and developing Verification Plan based on Specification
- Versatile and multi-skilled with ability to manage multiple responsibilities simultaneously, achieve defined goals & objectives, an effective communicator with Strong Problem Solving & Organizational Skills.
Timeline
SoC Design Engineer
Intel India Pvt Ltd
12.2019 - Current
Verification Engineer
AMD India Pvt Ltd
04.2016 - 11.2019
Verification Engineer
EnSilica India Pvt Ltd
10.2014 - 03.2016
Trainee Verification Engineer
ExpertHDL
08.2013 - 07.2014
Bachelors of Technology - Electronics And Communications Engineering
Bharat Institute of Engineering & Technology
07.2009 - 05.2013
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