Sai Pavan Kumar Kandregula

• Led the physical design of a high-performance 3M gate-count block with 128 macros operating at 960 MHz, driving floorplan-to-sign-off execution using Innovus and Fusion Compiler (FC), achieving robust congestion, timing, and sign-off closure under tight PPA constraints.
• Owned end-to-end block-level physical design from floorplan to sign-off (placement, CTS, routing, PDN, STA, PV, FV/CLP), delivering a fully clean block across multi-corner, multi-mode scenarios.
• Transformed a congestion- and timing-critical block by reducing global congestion from 1.29 to 0.13 through congestion-driven placement, block shape optimization, macro re-placement, and partial blockages; improved setup timing from 800 ps to 50 ps via Vt optimization and floorplan refinement.
• Resolved severe hold violations at CTS stage (-1.2 ns across 12 paths) by applying placement bounds and targeted optimization, achieving near-clean hold closure at -0.04 ns (40 ps).
• Reduced routing shorts significantly from 800 to 65 by optimizing port placement patterns and introducing routing blockages in high-density regions; achieved zero DRC and zero shorts during the ECO cycle.
• Drove sign-off quality timing closure by fixing max transition, max capacitance, crosstalk, antenna violations, and closed timing using Tweaker, DMSA, and PrimeClosure, ensuring robust cross-corner convergence.

• Working as a physical design engineer.
• Handled various aspects of physical design, such as floorplan, clock tree synthesis, and routing.

Project 3:

Role: Physical Design.

Design spec: 1 block with multi-voltage design, ~0.3M instance count, 8 macros, and operating with 1 GHz.

Tools: ICCOMPILER II (ICC2).

Client: AMD.

Roles and Responsibilities:

• Responsible for Place & Route, Timing, and PV closure. Resolved congestion issues during macro placement by following macro placement guidelines.
• Created PG regions for multi-voltage domain implementation. Performed a customized placement of level shifters.
• Taken care of analog routing and custom routes implementation. Successfully guided placement in macro channels with checker-box blockages.
• Worked on various sign-off issues while handling blocks such as CLP, UPF, and LEC. Addressed DRV fixes such as DRCs, LVS, and antenna during ECO implementation.

Project 2:

Role: Physical Design.

Design spec: 1 block with approximately 1M instance count, 20 macros, and operating at 1 GHz.

Tools: ICCOMPILER II (ICC2).

Client: AMD.

Roles and Responsibilities:

• Responsible for place and route, timing, and PV closure.
• Taken care of analog routing and custom route implementation. Taken care of supply sense blockages, and custom buffer placement.
• Addressed DRV fixes such as DRCs, LVS, and Antenna during ECO implementation.

Project 1:

Project: Integrating ProteanTecs IP into Block Register Transfer Level, and Improving the Quality of the ProteanTecs Solution.

• Worked on Digital VLSI as a Physical Design Engineer from RTL to GDSII.
• Hands-on experience in both Cadence (Genus and INNOVUS) and Synopsys (DC, ICC2, and PrimeTime) tools.
• Worked to improve and automate the RTL to GDSII Proteantecs flow.
• Tasks involved in finding bugs, and the root cause of bugs.