SAKETH ALLANI

Project 1 :

Role: PnR Execution

Technologies: TSMC 3nm, DFP, Low Power Techniques.

• Implemented ESC cells with combined boundary and tap cell functionalities to optimize macro-dominant tiles with limited area availability to meet Well or substrate tapping requirements.
• Resolved tool-induced sync cell Vt swap violations and corrected IO delay mis-scaling due to full-chip vs tile-level time unit inconsistencies, ensuring CDC integrity and accurate STA.
• Collaborated with the full-chip floorplan team to re-allocate area from my tile, redefined floorplan boundaries, and modified port relocation manually to ensure seamless integration with adjacent tiles in cold start run.
• Implemented split blockages in the macro channel to reduce high utilization and mitigate routing congestion.
• Achieved a Successfull reduction in clock latency by implementing magnet placement and clock balance point techniques, bringing latency down to 40% of the clock period.
• Implemented L-shaped, step-wise routing guides to decrease congestion near notches
• Executed ECO’s on 2 Tiles to resolve Low-Power design Issues and Improve Quality of Results.
• Resolved Dynamic IR Drop, Static IR, Electromigration, issues at ECO stage for 2 blocks.
• Addressed VSI issues like wrong domain placement and UPF related issues for 2 blocks.
• Did Manual Routing For 40 Setup - Hold Conflict Critical nets to resolve Long net violations at ECO Stage.

Project 2

Role: ECO Support.

Technologies: TSMC 3nm, Low Power Techniques.

• Automated ECO generation using custom TCL scripts for Getting Timing Margins and For Upsizing the cells, significantly improving turnaround time.
• Executed effective ECOs, resulting in a substantial decrease in DRV violations.
• Manually added buffers on nets outside LS regions to prevent cell displacement.
• Resolved Tap Cell Resistance issues on nets by manually adding parallel stripes to enhance power integrity.
• Resolved EM Issues By routing Shapes on HIgher Layers.

Here’s a polished, resume-style rephrasing for you:

• Developed ECOs for MV timing based on detailed timing analysis.

• Worked on Block of 20K Instances With No Predefined Flow (28nm).
• Completed the entire PnR flow for a block, which provided valuable industry exposure and helped me understand the challenges involved, along with strategies to effectively tackle them

• Experience in Java Coding For About 3 Months.