Saloni Shukla
Bengaluru
Summary
- More than 3 years of experience as a Physical Design Engineer.
- Experience in lower design nodes and various design technologies like 5nm, 7nm, 28nm, etc.
- Has Expertise in Physical Design flow stages like Synthesis, Floorplanning, Placement, CTS, Timing Closure, SI analysis, IR drop analysis, DRC/LVS, and ECO's (Functional and Metal).
- Block level timing closure and PV closure. Resolving various block-level P&R issues.
- Hands-on experience with various EDA tools.
- Ability to work independently as well as part of a team.
- Good Analytical, design and problem-solving skills.
Overview
2024
2024
years of professional experience
Work History
Physical Design Engineer
In house
- Entire Physical Design Flow from Netlist to GDSII
- Place stage issues with congestion and setup timing violation
- After Route OPT stage issues with shorts, DRCs, and Timing
Physical Design Engineer
Broadcom
06.2022 - 05.2023
- As a physical design engineer, in this project I was responsible for from Netlist to signoff
- As this partition was rectilinear in shape and more timing critical in all the interface partitions both the intra-inter timings are critical in this partition due to the greater number of ports communicating with the other partitions
- Initially I have seen few design issues, regarding that suggestion given to frontend team
- I have seen port placement issues for that interacted with top-level team
- To resolve timing issues interacted with the timing team
- To resolve congestion and timing issues, had taken multiple floorplan iterations
- Feedback given to RTL team due to excessive logic levels present in R2R paths, causing setup violations
- To resolve CTS stage issues have done multiple CTS experiments
- All the above analyses along with fixes were implemented on the initial netlist releases
- Implementation of the ECOs was the biggest challenge - with few ECOs having seen convergence issues, for the same have reverted to n-1 eco and re-implemented with updated ecos
- Initial flow flush shorts were huge - later n/l release i.e., later iterations shorts got fixed with density screens along with proper macro placements
- Participated actively in continuous improvement initiatives aimed at enhancing team efficiency and skill set growth.
- Developed custom scripts for improved design flow efficiency, boosting productivity within the team.
- Managed tape-out processes effectively, ensuring successful silicon production and customer satisfaction.
- Conducted rigorous timing analysis to guarantee accurate timing closure for complex digital designs.
Physical Design Engineer
Broadcom
01.2022 - 08.2022
- Floorplan, Power Plan, Placement, CTS, Routing, Timing Analysis, DRC Checks
- Block is timing critical
- Timing Enclosure, Analysis of various reports and fixes
- I have seen bad qor due to a few paths which were not optimized properly - later addressed these issues resolved with path group weightages
- Building CTS was a bit challenging as there are multiple clocks
- Grouped a few clocks to attain better skew and timing
- Initially most of the timing violations were fixed with GBA analysis, the rest of the violations was fixed with PBA mode analysis
- Faced Antenna violations, fixed using antennal diode insertion
Physical Design Engineer
Broadcom
09.2022 - 05.2022
- Floorplan, Power plan implementation, Placement, CTS, routing and Timing, and Physical verification closure
- Have done multiple iterations of the floorplan and port placement
- Initially have seen placement stage congestion and timing issues at the corners and mouths of the macros
- The major challenge was balancing the skew and minimizing the latencies
- In my design I have seen sudden utilization jump place to CTS at an initial run
- Later runs corrected cts structure by fine-tuning the clock tree spec file
- I got very good results with allowing single-cell clock tree building, even my qor also improved
- Routing DRCs over the mouth of Macros
- Manual efforts on fixing DRCs and shorts
- Fixed Antenna Violations with insertion of antenna diode
Education
B Tech - Electronic And Communication
Rajiv Gandhi Prodyogiki Vidhyalay
Bhopal07-2017
Skills
- Design Compiler
- ICC2
- Innovus
- Primetime
- Caliber
- TCL
- Unix
- Windows
Disclaimer
I hereby declare that the above information is true and correct to the best of my knowledge.
Projects
Block-Level P&R Implementation, Broadcom, TSMC 5nm/15 Layers, 62/1.4M, 1 GHz, 5 (2 Main, 2 Generated, 1 Virtual), 486.951 x 613.92 sq.mm, FC, Prime Time, 06/01/22, 05/31/23, 11, As a physical design engineer, in this project I was responsible for from Netlist to signoff., Initially I have seen few design issues, regarding that suggestion given to frontend team., I have seen port placement issues for that interacted with top-level team., To resolve timing issues interacted with the timing team., To resolve congestion and timing issues, had taken multiple floorplan iterations., Feedback given to RTL team due to excessive logic levels present in R2R paths, causing setup violations., To resolve CTS stage issues have done multiple CTS experiments., All the above analyses along with fixes were implemented on the initial netlist releases., Implementation of the ECOs was the biggest challenge - with few ECOs having seen convergence issues, for the same have reverted to n-1 eco and re-implemented with updated ecos., Initial flow flush shorts were huge - later n/l release i.e., later iterations shorts got fixed with density screens along with proper macro placements. Block level netlist to GDSII implementation, Broadcom, TSMC 7nm/12 Layers, 42/815K, 1.5 GHz, 6 (2 Main, 2 Generated, 2 Virtual), 399.93 x 499.92 sq.mm, FC, Prime Time, 09/01/22, 05/31/23, 9, Floorplan, Power plan implementation, Placement, CTS, routing and Timing, and Physical verification closure., Have done multiple iterations of the floorplan and port placement., Initially have seen placement stage congestion and timing issues at the corners and mouths of the macros., The major challenge was balancing the skew and minimizing the latencies., In my design I have seen sudden utilization jump place to CTS at an initial run. Later runs corrected cts structure by fine-tuning the clock tree spec file. I got very good results with allowing single-cell clock tree building, even my qor also improved., Routing DRCs over the mouth of Macros., Manual efforts on fixing DRCs and shorts., Fixed Antenna Violations with insertion of antenna diode. Block-Level P&R Implementation, Broadcom, TSMC 7nm/13 Layers, 28/910K, 850 MHz, Innovus, FC, Primetime, 420.82 x 500.56 sq.mm, 8, Floorplan, Power Plan, Placement, CTS, Routing, Timing Analysis, DRC Checks., Block is timing critical., Timing Enclosure, Analysis of various reports and fixes., I have seen bad qor due to a few paths which were not optimized properly - later addressed these issues resolved with path group weightages., Building CTS was a bit challenging as there are multiple clocks. Grouped a few clocks to attain better skew and timing., Initially most of the timing violations were fixed with GBA analysis, the rest of the violations was fixed with PBA mode analysis., Faced Antenna violations, fixed using antennal diode insertion. Block-level PnR Implementation, In house, TSMC 28nm/9 Layers, 20/630K, 650 MHz, ICC2, PT, 6, Entire Physical Design Flow from Netlist to GDSII., Place stage issues with congestion and setup timing violation., After Route OPT stage issues with shorts, DRCs, and Timing.
Timeline
Physical Design Engineer
Broadcom
09.2022 - 05.2022
Physical Design Engineer
Broadcom
06.2022 - 05.2023
Physical Design Engineer
Broadcom
01.2022 - 08.2022
Physical Design Engineer
In house
B Tech - Electronic And Communication
Rajiv Gandhi Prodyogiki Vidhyalay
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