Experienced RTL Design Engineer with a strong foundation in Digital Electronics and Signal Processing, specializing in the development, integration, and validation of complex Digital Logic Designs. Proven expertise in RTL design and microarchitecture development for high-performance signal processing algorithms, with a particular focus on 5G NR PHY Layer 1 implementation. Adept at translating complex system requirements into efficient, optimized hardware architectures. Collaborates effectively with cross-functional teams, including verification engineers and embedded developers, to deliver robust and scalable hardware solutions. Passionate about VLSI and next-generation telecommunication technologies, with a commitment to advancing cutting-edge digital hardware systems.