Sampath Govardhan Kukunuri
Sangareddy
Summary
Experienced RTL Design Engineer with a strong foundation in Digital Electronics and Signal Processing, specializing in the development, integration, and validation of complex Digital Logic Designs. Proven expertise in RTL design and microarchitecture development for high-performance signal processing algorithms, with a particular focus on 5G NR PHY Layer 1 implementation. Adept at translating complex system requirements into efficient, optimized hardware architectures. Collaborates effectively with cross-functional teams, including verification engineers and embedded developers, to deliver robust and scalable hardware solutions. Passionate about VLSI and next-generation telecommunication technologies, with a commitment to advancing cutting-edge digital hardware systems.
Overview
3
3
years of professional experience
1
1
Certification
Work History
Project Associate 5G Testbed R&D
Indian Institute of Technology
Hyderabad
12.2023 - Current
- Worked on Fixed and Floating point formats.
- Worked on third-party IP integration as per project requirements.
- Worked on RTL design of FFT, Matrix multiplication and Matrix Inversion modules.
- Involvement in the IP integration and developed the required scripts for testing purposes.
- Implemented debugging frameworks, significantly improving debugging capabilities across multiple clock domains.
Project Staff 5G Testbed R&D
Indian Institute of Technology
Hyderabad
08.2022 - 11.2023
- Responsible for generating linting and timing reports of RTL IPs.
- Developed automation scripts to streamline the FPGA design flow, and implemented a comprehensive testing framework using Questasim, improving design verification efficiency and reducing debugging time.
Education
Bachelor of Technology - Electronics and Communication Engineering
Sreenidhi Instuite of Science and Technology
Ghatkesar, Telangana07.2022
Intermediate (Class XII) - MPC
Narayana Junior College
Hyderabad, Telangana04.2018
SSC(Class X) -
Krishnaveni High School
Sadasivpet, Telangana04.2016
Skills
- HDL: Verilog, System Verilog
- Scripting: Python, Shell, Bash, TCL, GNU Make
- Programming: C, C, Python
- Tools: Intel Quartus, Xilinx Vivado, Questasim
- Microarchitecture design and development
- Good understanding of RTL design trade-offs (Fmax, latency, throughput, area, and power)
- Worked on multiple clock domains, STA/CDC, setup, and hold time constraint developments
- Knowledge of AMBA AXI, APB, SPI, I2C, and UART
- Working knowledge on HPS, DDR, DMA, Ethernet on FPGA
Projects
- mmwaveUE (08/2022-08/2024 ): Worked on IP Integration and testing, clock domain used - 247.56 MHz and 400 MHz.
- ULPI (09/2024-Present): Working on RTL development of Open-RAN Massive MIMO solution, clock domain used - 491.52 MHz.
Certification
- Data handling and hardware programming ( Aug 2022 - Nov 2022)
- Signal Processing and Embedded Systems (Dec 2022 - Feb 2023)
- GATE 2024
Timeline
Project Associate 5G Testbed R&D
Indian Institute of Technology
12.2023 - Current
Project Staff 5G Testbed R&D
Indian Institute of Technology
08.2022 - 11.2023
Bachelor of Technology - Electronics and Communication Engineering
Sreenidhi Instuite of Science and Technology
Intermediate (Class XII) - MPC
Narayana Junior College
SSC(Class X) -
Krishnaveni High School
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