Sanchit Gupta

• Focused on validating key PDK components, including CDS (pcell), LVS, DRC, parasitic extraction, and SPICE simulations, by developing SKILL-based automation to generate comprehensive schematic and layout test cases for all available devices with various parameter combinations. Ensured seamless integration and proper handshake between components by consolidating test cases into a TOPCELL for thorough verification.
• Demonstrated expertise in CDS validation, with a deep understanding of PCell structures, device physics, guard rings/taps, callbacks, and well definitions. Proven experience in validating PDK device libraries to ensure design integrity and industry compliance.
• Proficient in LVS verification and debugging of stamping, shorts, and device issues; skilled in SVRF rule interpretation and troubleshooting.
• Extensive hands-on experience in creating test benches and executing both pre- and post-silicon simulations in Cadence ADE, using HSPICE and Spectre models. Skilled in simulation setup, result analysis, and efficient debugging to ensure accurate and reliable circuit performance.
• Proficient in device-level DRC verification, including the identification and resolution of design rule violations to ensure compliance with foundry requirements, and robust manufacturability.
• Executed comprehensive parasitic extraction flows using multiple EDA tools, generating and validating extraction results to ensure accurate device modeling and circuit verification.
• Designed and maintained a Python-based GUI to streamline multi-switch DRC across multiple technologies, significantly boosting flow coverage. Automated verification workflows using shell scripts improve efficiency, scalability, and consistency in semiconductor design processes.
• Implemented and tailored skill-based automation for LSI node flows, increasing test case coverage by 90%. Spearheaded the development of algorithms and tool flows for efficient input file generation, streamlining, and accelerating the overall verification process.
• Working Node/Tech: Planar FETs, Fin FETs, BCD, PMIC, FDSOI, ESD, etc. (3nm-180nm).

• Generated a comprehensive test case database encompassing all devices in the library using Cadence Virtuoso.
• Ensured thorough parameter coverage by systematically varying all relevant parameters across test cases.
• Incorporated all available fluid guard rings and wells into test cases to validate their functionality and integrity.
• Developed automation scripts to generate and format input files for flow verification, ensuring compatibility with verification tools.
• Analyzed verification results and provided actionable feedback to the team, driving improvements in coverage and process quality.

GPA: 8.31