SANDEEP KOTHURI
Silicon Validation Engineer
Guntur
Summary
Equipped with strong problem-solving abilities, willingness to learn, and excellent communication skills. Poised to contribute to team success and achieve positive results. Ready to tackle new challenges and advance organizational objectives with dedication and enthusiasm.
Overview
13
13
years of professional experience
9
9
years of post-secondary education
Work History
Validation Engineer
INTEL
Bangalore
10.2018 - Current
- Post-silicon validation (Server processor)
- Reset Validation
- Reset IP is the HW responsible for booting the silicon
- Worked on status_scope reset plug-in scripts
- Understanding of the Reset flows
- Validation of features like Cold Reset, Warm Reset, Global Reset, Surprise Reset, IP disables boot flows
- Post-silicon validation (Client/PC processor)
- PCIe Validation
- PCIe Interface Validation: Led the post-silicon validation efforts for high-speed PCIe Gen 3/4/5 interfaces on cutting-edge semiconductor products, ensuring compliance with PCIe specifications and interoperability with various devices
- Test Planning & Execution: Developed comprehensive validation test plans, including stress testing, corner case testing, and performance benchmarking, to validate the functionality and reliability of PCIe-based systems in real-world use cases
- Hardware Debugging: Utilized advanced debugging tools (e.g., logic analyzers, protocol analyzers, oscilloscopes) to troubleshoot and resolve hardware-related issues and ensure correct signal integrity and data transmission between PCIe devices
- Performance Tuning: Analyzed and optimized system performance to ensure data throughput met design specifications, identifying bottlenecks and implementing solutions to improve latency and throughput
- Automated Test Development: Created and maintained automated test scripts using languages such as Python to streamline validation processes and ensure repeatability of test cases
- UFS Validation
- UFS is a flash storage protocol used in consumer electronic devices
- Validated UFS 2.1/3.0 protocol features like data transfer tests, power management tests, stress tests, performance tests with different devices across multiple projects
- Supported UFS Debugs using TLA and oscilloscope
- Responsible for enabling automation scripts
- Enabling of Automation tool which can automate test case execution on different platforms, collection of logs and post failure analysis
- Documented entire validation process, noting changes or alterations completed.
- Mentored junior engineers in best practices for validation engineering methodologies improving team skillsets.
- Implemented continuous improvement initiatives for validation processes, leading to enhanced product quality and cost savings.
Validation Engineer
QUALCOMM
Bangalore
02.2016 - 09.2018
- Worked on below peripheral blocks pre and post silicon validation on multiple projects at Qualcomm:
- QUP
- QUP block covers the slow speed peripherals like I2C, SPI, UART and I3C
- Validated protocol features like data transfer tests, stress tests, Interrupts and frequency tests on both pre and post silicon validation
- Providing drivers to the team for integration in their test cases
- TLMM
- TLMM (top-level mode multiplexer) is a block which is used for GPIO muxing with different function selects
- Validation of Interrupts and debug bus on post-silicon
- Providing drivers to the team for integration in their test cases
- UIM
- This UIM controller is used for communication with the SIM card
- Validation of protocol features like ATR tests, Interrupts tests and power tests
- Audio - I2S, PCM
- Audio protocols are used for connecting digital audio devices together
- Validation of I2S includes tests at different sampling freq 32Khz,44.1Khz,48Khz and 96Khz, Interrupts tests, power collapse tests and AP box tests
- Validation of PCM includes tests at different sampling freq 8Khz,16Khz and 32Khz, Interrupts tests, power collapse tests and AP box tests
- Keypad
- Keypad controller is used for key press scanning
- Validation of controller features like first press, long press, repeat press, Interrupts with an 8
- 8 keypad
- Validation of Debug Bus in GPU block
- Debug bus is block which bring out the internal signals for debugging
- Understanding the possible features of Debug bus
- Debug bus data dump on silicon comparison with FSDB data (DV) for validating
- Using MISR validated GPU Internal signal transaction values
Validation Engineer
MICROSEMI
Hyderabad
10.2013 - 06.2015
- Validation - Programmer Hardware
- This project target is Hardware validation of Microsemi FPGA programmer which is called Flash pro
- This involves Signal Integrity testing, functional testing and stress testing
- Validation - SF2 Devices
- This project target is to validate the different Use cases of Specified protocol on different derivates of SF2 devices
- CAN - Basic TX and RX messages, 32 TX/RX FIFO, validated filters to receive data packets, Interrupts
- USB - Host Mode with PHY ULPI Mode
- Basic Write and Reads into the Pen drive
- Flash freeze - Flash freeze is a low power state where all the fabric logic is freezed and IO will have the previous value stored
- Entry of Flash freeze is validated through CM3 and Fabric
- DDR - CM3 accessing DDRC - PHY16, PHY32 different patterns like Incremental, walking ones walking zeros and Random
- FIC accessing DDRC - AXI, INCR Mode and 16 Bursts
- DDR controller Throughput
- This project target is to calculate the throughput for the DDR controller
- Run simulations with DDR controller Libraries and DDR3 memory Model and also verified the same on the silicon
- DDR transactions are done through the FIC I/F which is configured to AXI Bus
- Throughput is calculated for 100 Bursts with different Fabric to DDR ratios
- Cortex-M1 Subsystem Implementation
- This project target is to implement a CM1 based Subsystem which is targeted for Xilinx virtex7 device
- The Subsystem includes 64K Memory for storing code and another 64K Memory for general purpose RAM and SPI, UART peripherals
- Emulation - Virtex7 and Kintex Ultra scale
- This project target is to emulate the System controller which manages programming of the Soc FPGA device and handles system service requests from Fabric
- The Sub tasks includes porting of ASIC RTLs to Xilinx platform, timing closure, simulation of basic stuff like txev and UART and then running the Basic tests on the emulated platform
- Bring up activities of modules HPDMA, SPI, USI (User service I/F), Tamper, SCB, and JTAG
- Validated AES, SHA crypto functions using the NIST vectors
Validation Engineer
United Technologies Corporation
Hyderabad
08.2012 - 09.2013
- Company Overview: Hyderabad, India
- Hardware Analysis and Firmware implementation of Burner controller
- In this project, Burner control is automated through the Microcontroller C8015F580
- This project is safety critical system
- The safety is ensured by using two Microcontrollers
- One is the Main Controller which drives all the outputs and the other Microcontroller will validate the Main Microcontroller
- In this project, I have done coding in embedded C for the Microcontroller internal diagnostics like Power-on diagnostics, ROM diagnostics, RAM diagnostics, CPU diagnostics, timer diagnostics, interrupt diagnostics which will run in the background sequence
- The burner sequence will run in the foreground sequence
- I have analyzed the hardware circuits and tested it
- I have done code testing
- The tools used are VARIAC, Oscilloscopes, Probes for Hardware testing, LTSpice for circuit analysis, USB debug adapter for debug/programming the MCU, Keil Software for developing the code, VECTORCAST for code testing/validation
- Hyderabad, India
Education
M. Tech - Electronic Instrumentation
NIT Warangal
Warangal 08.2011 - 07.2013
B.Tech - ECE
Lakireddy Balireddy College of Engg
Mylavaram 07.2006 - 06.2010
XII -
Sri Chaitanya
Vijayawada 06.2004 - 05.2006
Class X -
Sri Sai Residential School
Tenali 06.2003 - 05.2004
Skills
Verilog
Disclaimer
I hereby declare that the information given above is true and correct., KOTHURI SANDEEP, 10/01/2023
Core Skills
VHDL, Verilog, Modelsim, IAR, Identify, Chipscope, Trace32, Actel Libero IDE, Xilinx Vivado, APB, AHB, AXI, CortexM1, CortexM3, C, Python Basics, Bugzilla, JIRA, SVN, Perforce, GIT, Windows, Linux
Timeline
Validation Engineer
INTEL
10.2018 - Current
Validation Engineer
QUALCOMM
02.2016 - 09.2018
Validation Engineer
MICROSEMI
10.2013 - 06.2015
Validation Engineer
United Technologies Corporation
08.2012 - 09.2013
M. Tech - Electronic Instrumentation
NIT Warangal
08.2011 - 07.2013
B.Tech - ECE
Lakireddy Balireddy College of Engg
07.2006 - 06.2010
XII -
Sri Chaitanya
06.2004 - 05.2006
Class X -
Sri Sai Residential School
06.2003 - 05.2004
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