Summary
Overview
Work History
Education
Skills
Accomplishments
Disclaimer
References
Timeline
Generic
Sandeep Nallagatla Sai

Sandeep Nallagatla Sai

Bengaluru

Summary

Accomplished Staff Engineer with a proven track record at Qualcomm, adept in EDA tools like Synopsys ICCompiler and Innovus. Spearheaded over 10 complex tape-outs, showcasing exceptional problem-solving skills and a knack for enhancing team knowledge. Excelled in cross-functional collaboration, significantly improving project timelines and product quality.

Overview

11
11
years of professional experience

Work History

Staff Engineer

Qualcomm
Bengaluru
03.2021 - Current
  • Joined as Lead Engineer Sr. In the CPU team, I was later promoted to Staff Engineer.
  • Handled over 10 complex tape-outs as lead, ensuring successful project completion and delivery.
  • Being part of the CPU team has guided the PD team on the floorplan issues, the placement of physical IPs, and router-related feedback.
  • Debugging and addressing DRC, ANTENNA, SOFTCHECK, ERC, and LVS checks, as well as other PV checks at different stages of the project, is helping the Physical Design team at the floor plan, routing, and tape-out stages for smoother PV convergence for core blocks.
  • In my role as a lead, I will close all the PV issues for all the HMs in the project and deliver them to SOC for all the runs. And driving the team to close all the pending ECOs/PDNs, along with all other PV checks.
  • Played a pivotal role in multiple programs by handling complex Hm's DRC closure without impacting timing and PDN.
  • Successfully executed manual ECO implementations across multiple projects, resulting in improved project timelines and reduced errors.
  • Ensured all PV checks were meticulously followed and completed.
  • Demonstrated strong attention to detail and problem-solving skills in managing and resolving net fixes.
  • Conducted basic PV training across all domains to ensure better convergence, enhancing team knowledge and collaboration.
  • Collaborated with cross-functional teams to identify and resolve PV-related issues, improving overall product quality.
  • Utilized advanced PV tools and techniques to enhance the accuracy and reliability of validation results.
  • Delivered in custom routing for critical nets from PLLs (3 GHz max frequency), and the temperature sensor carefully balancing the RC among those routes.
  • Worked with the PDN team to complete a custom RDL by implementing a Comb structure routing, significantly enhancing PDN robustness.
  • Enabled Innovus-based void filling for top layers, further improving PDN robustness.
  • Enabled and analyzed track-based utilization (QUA) for multiple projects, providing feedback to the PD team for better area utilization for upcoming programs. Leading to a more effective use of edges.
  • Worked on ZeroDRC Methodology to ensure the majority of PV checks were clean at the HM level by implementing correct and constructive methods in collaboration with CAD support.

Lead Engineer

Qualcomm
Bengaluru
08.2018 - 04.2021
  • Having worked for a Qualcomm client through Cerium systems Pvt.Ltd, I have engaged in cutting-edge PV activities for TSMC's 3nm and 4nm nodes, and I have worked on 5nm, 7nm, and 10nm as a Mask Design Engineer, providing critical early PV feedback and supporting full chip verification.ip verification.
  • Debugging and addressing DRC, ANTENNA, SOFTCHECK, ERC, and LVS checks, as well as other PV checks at different stages of the project, helping the Physical Design team at the Floor Plan, Routing, and tape-out stage for smoother PV convergence for core blocks.
  • In my role as a lead, I will close all the PV issues for all the HMs in the project and deliver them to SOC for all the runs. And driving the team to close all the pending ECOs/PDNs, along with all other PV checks.
    Planning the resource allocation and taking the necessary decisions to meet the tight timelines.
  • Handled antenna and density checks from the full chip level.
  • Involved in floor planning, routing, and sign-off activities for block-level implementation.
  • Developed skills in understanding the challenges of floorplan and the reduction of congestion hot spots without much impact on timing convergence.

Senior Physical Verification Engineer

Qualcomm
Bengaluru
02.2016 - 03.2018
  • In Qualcomm through Mirafra Technologies in the CPU/GPU cores team, taped out multiple projects in technology nodes like 14nm, 20nm, and 28nm (SAMSUNG/TSMC foundries) as a Physical Verification Engineer.
  • Debugging and addressing DRC, ERC, LVS checks, soft checks, and other PV checks at different stages of the project helps the Physical Design team at the floor plan, routing, and tape-out stages for smoother PV convergence for core blocks.
  • Achieved experience in handling complex Modem/Tiles/Multimedia/CPU cores, hard macros, and managing/training team members.
  • Provided technical support to other departments in resolving complex convergence-related issues.
  • I worked as a PD engineer on a couple of projects with the Multimedia team on floorplan activities for the wrapper level, and I delivered on time with high quality.
  • I have done pin placement, along with macro placement, by taking care of all PV hotspots by identifying them at early stages.
  • Identified opportunities for improving efficiency in the physical verification process through automation or other means by enabling correctness through constructive methods.

Project Engineer

Wipro Technologies
Bengaluru
12.2013 - 02.2016
  • Worked as Physical Verification Engineer for INTEL client on 14nm technology node
  • Handled Physical verification for Display section, which consists of multiple partitions, involved in activities of DRC/LVS and Timing ECO's implementation for blocks
  • Worked as Section level Lead with team of Freshers, managed projects effectively to deliver finished work on time

Education

Bachelor of Science - Electronics

Sri Venkateswara University
Tirupati
04-2013

Skills

EDA Tools:

  • Synopsys ICCompiler I/II
  • IC Validator
  • Caliber
  • Virtuoso
  • Innovus

Accomplishments

  • Received Appreciations and Awards in Wipro Technologies in meeting the Strict deadlines by handling complex Hard Macro's.
  • Received appreciations from Management for being a Good Mentor for new Joiners.
  • Received Qualstar award for multiple projects for delivering on-time with high quality.
  • Received “Impact Award” from the VP for handling complex PDN-aware net fixes and uplifting frequency by 50 MHz to meet Fmax Target through manual effort.

Disclaimer

I consider myself familiar with Electronics Science and Engineering aspects. I am also confident of my ability to work in a team. I hereby declare that the information furnished above is true to the best of my knowledge.

References

References available upon request.

Timeline

Staff Engineer

Qualcomm
03.2021 - Current

Lead Engineer

Qualcomm
08.2018 - 04.2021

Senior Physical Verification Engineer

Qualcomm
02.2016 - 03.2018

Project Engineer

Wipro Technologies
12.2013 - 02.2016

Bachelor of Science - Electronics

Sri Venkateswara University

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Sandeep Nallagatla Sai