Summary
Overview
Work History
Education
Skills
Websites
Certification
Interests
Personal Information
Training
Activities
Timeline
Generic
Sandipan Dey

Sandipan Dey

Analog Design Engineer
Dum Dum

Summary

As a developing Analog Design Engineer, to associate with a progressive organization which will give me a chance to explore my creative ideas, a scope to apply my knowledge and involve me as a part of the team that dynamically works towards the growth of the organization.

Overview

5
5
years of professional experience
4037
4037
years of post-secondary education
3
3
Certifications
3
3
Languages

Work History

Senior Analog Design Engineer

Excelmax Technologies (Accenture)
05.2024 - Current
  • I am designing loop based switch controller in 14nm technology
  • I have designed 2 capless LDO's for 6mA and 20mA load current, beta multiplier, reference buffer, Level shifter in 5nm technology
  • I have designed multi-voltage level-shifters, REFTOP (BGR, V2I, Host-DET, comparator) amplifiers in 14 nm technology
  • I have done post-layout verification, design verification and modification of 2 IP in 5nm technology, doing top-level verification (sim-plan creation, testbench creation, Debug issues and modification).

Analog Design Engineer

HCL Technologies Ltd.
07.2021 - 05.2024
  • Training- I have designed Charge Pump Regulator
  • ACDC convertor project- I have designed slow, fast, rail-rail comparators, V2I amplifier, LDO, reference and input buffer for CDAC. I have also performed various top-level simulations
  • AMOLED driver project(2 version)-Depending on the requirement I have redesigned current sense amplifiers, implemented powerFET segmentation, OCP, SCP etc. I have done top-level simulations, post-silicon issue debug and provided effective solutions
  • MEDTECH project - post-silicon issue debug and modifications. I have redesigned the charge monitor block for better accuracy, designed POR, modified LDO for a higher load, reduced DAC cathodic and anodic mismatch current, increased autocalibration accuracy etc.

Intern

HCL Tecnologies Ltd.
12.2020 - 06.2021
  • I have designed one capless LDO with improved transient response

Education

B. Tech - Electronics and Communication Engineering

Heritage Institute of Technology
07.2017 - 06.2021

Higher Secondary(12th) -

Dum Dum Kishore Bharati High School

Madhyamik(10th) -

Dum Dum Kishore Bharati High School

Skills

  • VLSI design
  • Analog Circuit Design
  • C,C,Python

Certification

NPTEL course on Analog Electronic and VLSI circuits and signals and systems

Interests

Painting
Audio books
Anime and Manga reading

Personal Information

Date of Birth: 10/29/99

Training

  • VLSI Design Engineering, ECOE, Odisha
  • Radio transmission and digital communication, AIR, Akashvani, Kolkata

Activities

  • Member of Science club and Aeronautics club in HITK
  • Member of COMPASS 2018 and 2019 in HITK

Timeline

Senior Analog Design Engineer

Excelmax Technologies (Accenture)
05.2024 - Current

Analog Design Engineer

HCL Technologies Ltd.
07.2021 - 05.2024

Intern

HCL Tecnologies Ltd.
12.2020 - 06.2021

B. Tech - Electronics and Communication Engineering

Heritage Institute of Technology
07.2017 - 06.2021

Higher Secondary(12th) -

Dum Dum Kishore Bharati High School

Madhyamik(10th) -

Dum Dum Kishore Bharati High School
Sandipan DeyAnalog Design Engineer