SANJANA BELDI
Hyderabad, Telangana 500034
Summary
- Experienced in Design Verification with almost 2 years of hands-on work.
- Expertise with UVM testbench development.
- Strong ability to design, develop, and debug testbenches and verification environments.
- Good at understanding and analyzing VIP environments.
Overview
3
3
years of professional experience
1
1
Certification
Work History
Functional Verification Trainee
VLSIguru
08.2022 - 04.2023
- Gained knowledge on Digital Circuits.
- Gained knowledge on Hardware Description language, RTL designs and building testbench.
Design Verification Engineer
Truechip Solutions
08.2023 - Current
NOC VIP (Aug 2023 - Jul 2024):
- Worked on on-chip interconnect protocols including AXI, AHB, APB.
- Created comprehensive test plans and developed both directed and dynamic test cases/sequences for new features.
- Debugging the issues posed by the design team to identify the root cause of the problem.
- Developed random and directed test cases to ensure full feature coverage.
- Implemented AXI monitor enhancements for NOC-specific error injection features.
DSI2 VIP (Oct 2024 – Feb 2025):
- Integration of the DSI VIP layer wise and provided support for the same.
- Implementation of the Display Pixel Interface between application and protocol layer.
- Implemented packet conversion logic between DPI and DSI2, along with checks in the scoreboard for the same.
UFS VIP (Feb 2025 – Apr 2025):
- Owner of the monitor component in the UFS VIP.
- Responsible for making check plan for the pending protocol features.
- Implemented application layer command checks in the UTP and UAP layers to validate protocol and packet behavior.
Education
B.TECH - Electronics and communication
Keshav Memorial Institute of Technology
Hyderabad07-2022
Intermediate -
Sri Chaitanya Jr college
Hyderabad04-2018
Sri Chaitanya school
Hyderabad03-2016
Skills
- Programming : Verilog, System Verilog, UVM
- Tools : QuestaSim, Xcelium
- C programming and Python
- Protocols: AXI,DSI2,UFS
Certification
Business English Certificate Cambridge Assessment September 2019
- CEFR LEVEL B1, score-149
GATE 2022 EC IIT Kharagpur February 2022
- Rank-5867, score-379
NPTEL Online Certification of Introduction to IoT - IIT Kharagpur
Jul-Oct 2023
- Score- Elite, Percentage: 69%
Timeline
Design Verification Engineer
Truechip Solutions
08.2023 - Current
Functional Verification Trainee
VLSIguru
08.2022 - 04.2023
B.TECH - Electronics and communication
Keshav Memorial Institute of Technology
Intermediate -
Sri Chaitanya Jr college
Sri Chaitanya school
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