Sanjana V Kulkarni - Senior Design Verification Engineer - Synopsys

Summary

Senior Design Verification Engineer with 3 years of experience in System Verilog/UVM-based verification and USB protocol verification. Experienced in USB 2.0, eUSB2 v1/v2, and USB 3.x VIP development, protocol debugging, feature enhancement, and regression analysis. Skilled in constrained-random verification, protocol compliance, and verification environment development, with a strong focus on adapting to AI-assisted workflows. Highly determined and performance-driven, with a continuous drive to learn, innovate, and contribute to high-quality verification solutions.

Overview

3

years of professional experience

Work History

Senior ASIC Digital Design Engineer

Synopsys

03.2023 - Current

1. USB 2.0/ EUSB2V2/V1

Co-owned USB 2.0 and eUSB2 v1/v2 VIP development across protocol, link, Remote PHY, and Local PHY layers. Enhanced VIP functionality to support evolving protocol specifications and feature requirements.
Investigated and resolved Host and Device side protocol issues in VIP behavior through detailed Verdi waveform analysis and root-cause investigation.
Owned development of protocol checkers and exception injection to strengthen VIP protocol checking and accelerate the verification of controller.
Supported VIP integration for eUSB2 v1, eUSB2 v2, and USB 2.0 Parallel Mode projects. Collaborated with design and verification teams to enable new protocol features in VIP releases.

2. USB 3.x

Contributed to 6+ USB 3.0, USB 3.1, and USB 3.2 controller releases by analyzing VIP behavior, debugging protocol issues, and implementing fixes to ensure release readiness.
Enhanced protocol and link-layer VIP functionality through feature development related to transfers, LTSSM state transitions, issue resolution, and behavioral improvements.
Resolved coverage-related issues by enhancing VIP sampling mechanisms and improving functional coverage accuracy.
Implemented protocol checks and analyzed Host, Device interactions to identify and resolve protocol and functional issues.
Developed an understanding of PHY-level behavior and its impact on protocol and link-layer functionality.

3. Development,Debug and Release Support

Investigated and resolved customer-reported and internally identified VIP defects through detailed debug, root-cause analysis, and implementation of critical fixes.
Co-owned VIP release support activities: executed regressions, analyzed incremental failures, identified root causes, and validated fixes prior to release signoff.
Debugged an average of 60+ VIP protocol and functional behavior per release cycle using Verdi waveform analysis, assertion violations, and checker logs. Drove root-cause fixes to improve regression pass rate pre-signoff.
Leveraged AI-assisted engineering workflows to accelerate debug, technical research, documentation, and engineering productivity.

Intern

Bosch Software Technologies

06.2022 - 07.2022

Gained exposure to automotive communication protocols including CAN, CAN-FD, Flex Ray, LIN, and Ethernet-based communication concepts.

Education

B.E - Electronics and Communication

B. M. S. College of Engineering

05.2023

Pre-University - PCMC

Sri Kumaran Composite PU College

Skills

Programming Languages: System Verilog, Verilog, Python
Verification: Constrained-Random Verification, Functional Coverage, System Verilog Assertions (SVA), UVM,VMM
Protocols: AXI4 Lite, eUSB2 v1/v2, USB 20, USB 3x

Interfaces: PIPE, UTMI, XHCI
Tools:Cursor, DVE, Git, Linux, Perforce, Verdi, VCS
USB VIP development

Websites

linkedin.com/in/sanjana-vkulkarni

Certification

Maven Silicon VLSI Design and Verification, 2023-02-01, 2023-05-01

Volunteering And Leadership

MAKE A DIFFERENCE: Volunteered for one year, mentoring and supporting underprivileged children through educational and developmental initiatives.
STEM REACH INITIATIVE: Led a team of four volunteers in designing and developing educational study modules for students. Coordinated content planning and task execution to ensure timely delivery of learning materials.

Hobbies and Interests

Scuba Diver (PADI Open Water Certified)
Trekking
Singing

Projects

AXI4 Lite UVM Verification Environment:

- Developed a reusable UVM testbench from scratch for AXI4-Lite protocol verification.

- Implemented UVM components including sequencer, driver, monitor, scoreboard, and agent.

- Developed constrained-random test scenarios to verify read and write transactions.

- Added functional coverage to measure protocol feature coverage.

- Debugged protocol and testbench issues using waveform analysis and UVM reporting.

- Implemented protocol assertions to verify AXI4-Lite handshake behavior.

FIFO Verification Environment:

- Developed a transaction-based System Verilog verification environment for synchronous FIFO verification.

- Implemented generator, driver, monitor, and scoreboard components.

- Verified FIFO functionality including normal operation, overflow, and underflow conditions.

- Applied constrained-random stimulus generation and self-checking mechanisms for functional verification.

Languages

English

Hindi

Kannada

German

Timeline