SANJAY BHATT

I am a recent college graduate with masters in Embedded Systems and Vlsi Design background, have strong understanding of digital design principles and foundational coding skills along with problem-solving, time-management, strong teamwork, communication and analytical skills. Worked on design, modeling, and simulation projects using industry-standard tools such as Xilinx Vivado and Cadence Virtuoso.

I am Prepared to start career and make meaningful contributions with commitment and drive.

Designing a 32-bit 5 stage pipelined RISC-V processor

• Developed a custom 32-bit MIPS (Microprocessor without Interlocked Pipeline Stages) RISC-V architecture prototype using HDL modelling of the logic circuits.
• Segmented the processor stages into instruction fetch, decode, execute, memory access and write-back for enhanced throughput.
• Exclusively managed Data hazards through hazard detection techniques and mitigated them through Data forwarding mechanisms ensuring smooth pipeline operation.

Designing a FPGA based car counting system for a parking lot

• Designed and implemented an FPGA-based system to count the number of cars in a parking lot.
• Implemented logic to increment or decrement the car count based on the input from the sensors and debounce the generated pulses from two push buttons on FPGA (i.e pressure senors) Generated a 4-bit signal "CarCount" as the output.
• The system was implemented using Verilog language and Xilinx Zedboard

8 bit Manchester Carry Chain Adder 

• Designed a High 8 bit area efficient and low power adder and also compared the performance of the designed adder with the conventional ripple carry adder using the Area*Delay product figure of merit(FOM).

Round Robin Arbiter/Scheduler citcuit

• Implemented round robin arbiter using verilog HDl and the code is implemented on EDA Playground.

Gate scholarship