Sanjay G M

Block / IP Level ::

• Physical Design Implementation (RTL to GDS) of channel Blocks (Including STA and EM/IR )
• Custom Clock Routing
• RDL / Bump Routing of both power and signal bumps
• Physical Signoff Activities
• Modification of Signoff deck to meet the needs of the foundary
• PERC Flow setup
• Good knowledge in understanding and modifying the PNR/PV flow as and when the requirement arises

SOC Level ::

• Floorplanning (Placement of the macros and getting the base_drc clean)
• RDL/Bump routing for both signal and power nets
• Placement of GPIOs and Alignment Markers based on the interposer feedback
• Subsytem and full-chip Integration along with phyical signoff (LVS , DRC and Tapeout )
• Hand's on experience in developing waiver for full-chip

Tech-nodes :: TSMC -16nm , 7nm , 5nm , 3nm

Samsung - S4

Tools :: ICC2 / Innovus (PnR) , Calibre (Physical Verification)

Block Level PNR ::

• ECO Implementation (Place and Route)
• IR Drop fixing using the markers based on the reports
• Density Fixes
• DRC and LVS fixes
• Delivering quality GDS

Tech-node :: Intel 14nm

Tools :: Internal tool of Intel (PARADE)

Block Level ::

• Physical Verification (DRC , LVS and other layout checks)
• Signal Integrity fixes
• IR Fixes

Tech-node :: Intel 10 nm

Tools :: ICC , ICV