Summary
Overview
Work History
Education
Additional Information
Reading Books, listening to music
Timeline
Sanjeev Joshi

Sanjeev Joshi

Physical Design Engineer
Banglore

Summary

Seeking a respectable position in a prominent organization that offers professional growth with mental satisfaction to utilize my skills and abilities while being resourceful innovative and flexible.

Overview

1
1
year of professional experience
6
6
years of post-secondary education
2
2
Languages

Work History

Physical Design Engineer

Scaledge Private Limited
Banglore
06.2022 - 06.2023
  • Worked on Intel 7nm node Project
  • Designed Block for Intel server chip 7nm
  • Responsible for handling block till apr_eco, extraction and other signoff flows.
  • Equipped with full PD design Flow from Import design to Physical Verification.

Education

Post Graduate -

Karnatak University
07.2018 - 05.2020

Msc - Electronics

GPA: 72

Graduate - undefined

C Jabin Science College
06.2015 - 05.2018

Bsc - Electronics

GPA: 74

Pre University - undefined

Sukruthi PU Science College
06.2012 - 05.2015

PUC - undefined

CHINMAYA VIDYALAYA
05.2010 - 05.2012
GPA: 67

SSLC - undefined

01.2020 - 05.2020
GPA: 72%, ) The main objective of the project was to implement a SVM code for different images of brain and to detect whether the tumor is present with accurate results. Here we are proposing a support vector machine technique to extract brain tumor with the help of image processing by implanting MATLAB .

Trained in VLSI - undefined

Chipedge Technologies
01.2022 - 05.2022
Complete understanding of PD flow from Netlist to GDS Synthesis, STA Analysis, OCV, Cross Talk Effects Floor Planning ,Power Planning, IR Drop Analysis CTS, Routing, Parasitic Extraction and Physical Verifi

cation SKILLS VHDl Basics of C C++ DC Compiler - undefined

05.2022 - 05.2020
Digital Ciricuits VLSI, Floor Planning PG Planning CTS Routing, Description: It was a block level design for 28 nm Technology with 4 clocks present in it and of 500MHz Frequency, with 16 Macro count and 300K Standard Cell count with 50% Core Utilization Tools Used: ICC2, Prime Time. Challenges: Basically the block is timing critical .Done various Experiments like Higher Metal layer Routing and Path grouping

JBI SPARC PROCESSOR - undefined

05.2022 - 05.2020
Description: It was a block level design for 28nm technology with a clock frequency of 700MHz, 46 Macro count, 32K Standard Cell count , 9 Metal layers and number of clocks 6. Complete physical design was carried out from Netlist to Routing which includes floor planning, power planning, placement, CTS, Routing, DRC checks and GDS report . Brain Tumor Extraction By Image Processing using MATLAB .

Additional Information

  • rotsan apartment Near vigneshwar school, old income tax office vidyanagar hubli, Hubli

Reading Books, listening to music

I love to read Indian Fiction mythology books

Timeline

Physical Design Engineer - Scaledge Private Limited
06.2022 - 06.2023
- cation SKILLS VHDl Basics of C C++ DC Compiler,
05.2022 - 05.2020
- JBI SPARC PROCESSOR,
05.2022 - 05.2020
Chipedge Technologies - Trained in VLSI,
01.2022 - 05.2022
- SSLC,
01.2020 - 05.2020
Karnatak University - Post Graduate,
07.2018 - 05.2020
C Jabin Science College - Graduate,
06.2015 - 05.2018
Sukruthi PU Science College - Pre University,
06.2012 - 05.2015
CHINMAYA VIDYALAYA - PUC,
05.2010 - 05.2012
- Msc, Electronics
- Bsc, Electronics

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Sanjeev JoshiPhysical Design Engineer