Sanket Gajjar
Ahmedabad
Summary
Equipped with strong problem-solving abilities, willingness to learn, and excellent communication skills. Poised to contribute to team success and achieve positive results. Ready to tackle new challenges and advance organizational objectives with dedication and enthusiasm.
Overview
12
12
years of professional experience
Work History
Principal Software Engineer
Cadence Design Systems
02.2023 - Current
- Led a multidisciplinary team of four in the end-to-end verification of DDR5 SDRAM and DDR5 MRDIMM models, ensuring timely, high-quality delivery through effective delegation and coordination.
- Directed customer support initiatives and managed complex test plan development for MRDIMM features, improving client satisfaction and reducing escalations.
- Oversaw coverage generation and analysis, mentoring junior engineers and driving process improvements.
- Facilitated cross-functional collaboration with design, development, and client teams to align verification goals with business objectives.
- Implemented best practices in risk assessment, resource planning, and technical troubleshooting, acting as a key escalation point.
Senior Verification Engineer
Nvidia Graphics Pvt. Ltd.
07.2021 - 02.2023
- DRAM verification, regression debugging, backdoor memory/register access implementation.
- Developed test cases for POR and automated regression test plans.
- Created end-to-end scoreboard infrastructure.
Component Design Engineer
Intel India Pvt. Ltd.
07.2019 - 06.2021
- Memory IP enablement lead supporting digital design flow.
- Verification lead for automated memory verification flow ensuring quality delivery.
- Developed SystemVerilog verification environment impacting RTL improvements.
Senior Verification Engineer
PerfectVIPs (ScaleEdge)
06.2017 - 06.2019
- IP Verification lead for Queue block, MACsec Subsystem, DDR Subsystem Software Lib.
- Developed VPLAN and COV PLAN.
- Integrated testbench, AXI4-Lite VIP.
Design Engineer II
AMD India Pvt. Ltd.
12.2016 - 05.2017
- DFT Verification of Multiple Core SoC Design.
- Created C-based test cases, POR feature checker.
Design Engineer I
Freescale Semiconductor (NXP), Noida
06.2013 - 10.2016
- Functional and gate level verification of SoC and memory IP interfaces.
- Trainee Design Engineer
- DDR3 controller register verification, BIST pattern development.
Education
M.Tech - VLSI Design
Nirma University
01.2014
BE - Electronics & Communication
LDRP Institute of Technology & Research
01.2011
Skills
- Verification & Simulation: Test plan development, coverage analysis, debugging, UVM environment creation
- Proficient in DDR and AMBA protocol standards
- Languages: Verilog, SystemVerilog, SVA
- Tools/Frameworks: VCS, IUS, Verdi, UVM, VMM
- Team Training
- Project planning
Timeline
Principal Software Engineer
Cadence Design Systems
02.2023 - Current
Senior Verification Engineer
Nvidia Graphics Pvt. Ltd.
07.2021 - 02.2023
Component Design Engineer
Intel India Pvt. Ltd.
07.2019 - 06.2021
Senior Verification Engineer
PerfectVIPs (ScaleEdge)
06.2017 - 06.2019
Design Engineer II
AMD India Pvt. Ltd.
12.2016 - 05.2017
Design Engineer I
Freescale Semiconductor (NXP), Noida
06.2013 - 10.2016
BE - Electronics & Communication
LDRP Institute of Technology & Research
M.Tech - VLSI Design
Nirma University
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