Santhosh Kumar
Analog Layout Expert
Bengaluru ,Karnataka
Summary
Analog/Custom Layout Expert with more than 13 years experience in managing complete product development life-cycle starting with initial scheduling, resource allocation, area estimation, floor-plan development, IP layout design, integration, physical verification, foundry communication, JDV review and post silicon support.
Overview
6
6
years of post-secondary education
14
14
years of professional experience
Work History
Layout Lead
Analog Devices
05.2019 - Current
- Develop, approve and coordinate work schedules to ensure that objectives of cost, quality and time are met
- Responsible for layout from transistor to chip level delivery on two successful product tape-outs.
- Leading and managing team to build RF analog layouts.
- Full chip pad-ring decisions with complete ESD compliance.
- Prepare packaging technical files and support feasibility analysis. Responsible for final PV approvals, foundry communication and JDV approvals.
Principal Engineer
Western Digital, SanDisk
12.2011 - 05.2019
- Responsible for end to end delivery of complete Analog Layout solutions for all ASIC controllers.
- Managed resource allocation, Project scheduling, Hiring, Tool evaluation, Infrastructure management and License management.
- Responsible for final sign-off and review on physical verification of SoC.
- Cost reductions strategies implemented by area optimization of controllers, utilizing different development tools.
- Managed various vendors for resourcing contractual positions.
- Reduced layout cycle time by working on full chip porting from foundry to foundry.
- Lead various CAD activities involving automation and process improvements.
Consultant
Ascent Consultancy
04.2011 - 12.2011
- Responsible for full chip layout delivery.
- Work on layouts of IPs such as ADLL, PLL and regulators in 40nm.
- Revise existing tools to amend errors, adapt to new hardware that ameliorated its performance.
- Perform test and modify design to meet client engineering demands.
- Managed multiple tape-outs in parallel to achieve internal milestone.
Project Engineer
Wipro Technologies
10.2007 - 04.2011
- Interact with customers to understand project requirements.
- Visit client organization periodically to work on critical tape outs.
- Work with esteemed client organizations like PMC, TI and ST on their critical projects.
Education
Master of Science - Microelectronics
Manipal University
Distance Education 05.2009 - 05.2011
B.E - Instrumentation
M.S. Ramaiah Institute of Technology
Bengaluru, KA 10.2003 - 06.2007
Skills
Tape-outs in various Foundry Technologies
Managed large Teams on multiple Projects
Expert in Physical Verification Methodology, PDK and Rule Deck Customization
Proficient in Power Management, Clocking and RF Modules
PATENT AWARDED
Awarded Patent in 2015 on MoM Capacitor Structure for Lead Inventor. USPTO Number: US 9,209,240.82
Timeline
Layout Lead
Analog Devices
05.2019 - Current
Principal Engineer
Western Digital, SanDisk
12.2011 - 05.2019
Consultant
Ascent Consultancy
04.2011 - 12.2011
Master of Science - Microelectronics
Manipal University
05.2009 - 05.2011
Project Engineer
Wipro Technologies
10.2007 - 04.2011
B.E - Instrumentation
M.S. Ramaiah Institute of Technology
10.2003 - 06.2007