Santhosh Yennamsetti Venkata

I am currently working with Qualcomm on Advanced Mobile Chips as Physical Design and STA Lead. Prior to this, I worked on Intel and AMD Graphics Chips as PD and STA Lead. Overall, 12 years of experience in Physical Design with 20 tape-outs across 2nm,3nm,4nm, 5nm,7nm ,10nm,14nm & 28nm
technological nodes.
Enthusiastic Physical Design Engineer eager to contribute to team success through hard work, attention to detail
and excellent organizational skills. Motivated to learn new things.

QUALCOMM EXPERIENCE (6 projects):

• Leading STA closure with a 4-member team on a 3nm node. Collaborating with constraints/design teams, experimenting with CTS and PNR settings, and delivering technical training on ECO best practices.
• Independently handled a complex, high-instance block with multiple power domains and critical timing/congestion issues. Delivered all signoff fixes, resolved DRC/shorts using route corridors, and supported the internal team.
• Led a 4-member team while owning a critical block. Handled critical issues debug, ensured milestone alignment via daily sync ups, and coordinated with stakeholders to resolve dependencies.
• Managed a team of 5 across 8 blocks. Led debugging and ECO delivery for TDRC, PV, and PDN issues, ensuring timely convergence.
• Took over a 4M instance block mid-project in a critical state. Devised and presented convergence strategies, tackled 10lm and FT buffering challenges, and earned management appreciation.

INTEL EXPERIENCE(4 projects)

• Project #1: Timing and quality owner for DDR partitions (~1.4M gates each) on 7nm TSMC, 1GHz. Delivered timing and DRV closure using ICC2 and PrimeTime. Tackled functional ECOs, IR issues, and skew-related timing challenges. Applied cloning and fanout split techniques for clock/data transition fixes.
• Project #2: Section execution and quality owner for 8 ON/OFF partitions (~700k gates each) on 10nm Intel Foundry. Led 7 engineers to achieve timing, IR, and DRV closure. Reduced DRC/shorts and coordinated with offshore teams for faster convergence.
• Project #3: Section timing and quality owner for 5 ON/OFF partitions (~700k gates each) on 10nm Intel Foundry. Led 5 engineers. Resolved interface timing violations in A0 stepping, automated hold fixing, and collaborated with global teams.
• Project #4: Section timing and quality owner for 9 ON/OFF partitions (~700k gates each) on 10nm Intel Foundry. Led 8 engineers. Ramped up quickly, addressed B0 stepping hold violations, optimized buffer usage in congested areas, and reduced DRC/shorts through advanced techniques and cross-site coordination.

AMD EXPERIENCE(8 projects):

• Project #1: Full-Flow Ownership of 1.8M & 710K Gate Blocks (14nm, Global Foundry)
  Handled two ON/OFF blocks from floorplanning to GDSII using ICC2, PrimeTime, Calibre, and Formality. Delivered timing, DRV, and DRC-LVS closure for highly congested and timing-critical designs. Addressed port movement issues during ECO stage and collaborated with PV team to automate DRC fixes.
• Project #2: P&R and Closure for 1.4M & 900K Gate Blocks (14nm, Global Foundry)
  Executed full P&R flow and closure for two ON/OFF blocks with 65 and 52 macros respectively. Conducted experiments on clock transition targets and corner enablement to optimize QoR. Resolved timing and routing challenges using advanced techniques.
• Project #3: Timing-Critical Block Closure (890K & 710K Gates, 14nm)
  Managed two ON/OFF blocks using First Encounter, IC Compiler, PrimeTime, and Calibre. Developed custom scripts for timing improvement during ECO stage. Delivered closure for blocks with high macro density and routing complexity.
• Project #4: P&R and ECO for 600K & 800K Gate Blocks (28nm, TSMC)
  Led P&R and ECO efforts for two ON/OFF blocks with 100 and 15 macros. Applied path grouping, clock gate pulling, and clock skewing to improve insertion delays and timing. Focused on DRC-LVS closure during ECO stage for physically critical blocks.
• Project #5: Manual Routing and Useful Skew for Timing Fixes (28nm, TSMC)
  Delivered full P&R flow for two AON blocks (600K & 700K gates). Used manual routing in Encounter and useful skew techniques to resolve timing and DRC issues during ECO.
• Project #6: Multi-Block Closure and ECO Support (28nm, TSMC)
  Handled two ON/OFF blocks (500K & 600K gates) and supported ECOs for four additional blocks. Delivered full P&R and closure, including timing, DRV, and DRC-LVS. Applied advanced techniques to meet timing in highly critical designs.
• Project #7: Congestion-Heavy Block Optimization (20nm, Global Foundry)
  Managed two AON blocks (280K gates and a smaller block) with high macro density. Tackled severe congestion and timing issues from placement stage onward. Delivered full flow using ICC, SoC Encounter, PrimeTime SI, and Calibre.
• Project #8: Design and Application of Programmable Delay Cell
  Designed a programmable delay (PDLY) cell from RTL to GDSII for ECO efficiency. Demonstrated improved timing control over traditional buffer chains. Addressed non-linear delay behavior with custom logic and manual routing of selection lines

I hereby declare that the above information furnished is true and correct to the best of my knowledge.

                                                                                                                                                        - Y V Santhosh