Santosh Mahale

Professional with over 13 years of experience in ASIC IP, sub-system, and SoC level verification. Expertise in ARM/RISC-V processor-based subsystem, PCIe Gen 2.0 and 3.0, AXI4, and APB4 protocols, along with functional safety verification through fault simulation. Proficient in utilizing System Verilog and UVM methodology for effective IP and SoC verification.

• Presented technical paper in DVCon India conference and won the First Runner up Prize, September 2023 - September 2023, Paper Title : Breaking Down Barriers: Seamless Protocol Conversion with UVM Component Layering.

Link : https://dvcon-proceedings.org/document/breakingdown-barriers-seamless-protocol-conversion-with-uvmcomponent-layering-2/

• Presented Technical Poster in DVCon India conference, September 2024 - September 2024, Poster Title: Synergizing Functional Safety and Fault Simulation: Towards robust and reliable systems in safety-critical SoCs.
• Got core value award at eInfochips
• Got the Pat On The Back award four times for executing the project as per the customer requirements and delivered on time at eInfochips
• Got shining start of the month award at Wipro

https://www.linkedin.com/in/santosh-mahale-verification/

Project.1: Full Chip Verification Of NIC (Network Interface Card) SoC.

Duration: 10 months

Methodology: System Verilog, UVM, C

Description: The NIC is a System-on-Chip (SoC) designed to convert data received over Ethernet into a PCIe interface for the host system. I was responsible for full-chip level verification of one of its key subsystems, which handles the chip's boot process. This subsystem includes three RISC-V processors:

Primary Boot Processor – initiates the basic boot sequence.

Secure Boot Processor – ensures trusted and authenticated booting.

Application Control Processor – executes the chip’s application firmware.

The SoC architecture comprises multiple subsystems, including:

• Network-on-Chip (NoC) subsystems
• Peripheral subsystems
• Security subsystem
• PCIe subsystem
• Ethernet subsystem
• Memory subsystems such as RAM and ROM.

Responsibilities:

• Developed a Full chip level testplan for the processor subsystem.
• Setup an system verilog UVM as well as C infrastructure for real core simulations.
• Worked on to setup a methodology to run the system verilog test & real core C test simulation.
• Verify the verif boot sequence on RISC-V processor.
• Verify the mailbox functionality to communicate between these 3 processors with real core simulations.
• Setup a flow for the ISR execution.
• worked on the interrupt verification with real core scenarios

Project.2 : Automotive Safety Island Sub System Verification

 System Verilog UVM Methodology, 

11 Months, 

Description : Safety Island is a subsystem which is going to sit in an automotive SoC chip, which is responsible for performing safety related functions and is designed with the goals of ASIL-D. The safety island monitors and logs faults from the application island and serves as a watchdog for the application island. In addition, the safety island can receive data from sensors over CAN, and can control the chassis by sending output commands over CAN., I am part of Safety Island subsystem level verification team. Our team's responsibility is to verify complete subsystem with all control paths as well as all the data path with 100% coverage goals and provide the bug free subsystem to Full chip team. Below are my 

Responsibilities: 

• Developed the subsystem level TB infrastructure from scratch.
• Integrated third party VIPs in to the env. 3. Developed env such that it can be reused at fullchip level TB.
• Developed few verification TB component i.e., DMA scoreboard, memory data scoreboard, functional safety monitor interface etc.
• Reused the VIP sequences at subsystem level env.
• Developed test cases for various Datapath's as well as control path verification.
• Implemented testplans for the IPs which I own in subsystem.
• Developed the TB infrastructure to reuse the test cases as it is from one of the lower-level IP which is integrated into our subsystem.

Project.3 : Block level verification of Control Processor Cluster

System Verilog UVM Methodology, 

1.5 Years, 

Description : The Control Processor Cluster (CPC) block contains the block contains the 4 ARM CM7 cores. all four cores have different functionality. Core0 (System Control Processor) : Runs BL0 boot sequence. It boots the system on chip and runs the trusted firmware. Core1 (Management Control Processor) : Booted by core0 and runs un-trusted firmware and also performs un-trusted management tasks. Core2 (Ethernet Control Processor) : Booted by Core0 and controls real-time link and serdes event control, autonegotiation and serdes training and monitor link performance. Core3 (PCIe Config Offload Control Processor) : Booted by Core0 and use to offload pcie config registers., 

Responsibilities: 

• Developed TB infrastructure and other verification collaterals.
• Developed CM7 stub verification infrastructure and developed various test cases for the same to achieve better functional coverage using more randomization.
• Perform the block level verification of registers with different scenarios i.e. reg walk pattern, reg bit bash, default value check, non existing reg space and different access sizes etc.

Project.4 : Server SoC Verification 

System Verilog UVM Methodology 

2.5 Years, 

Description : Server-class microprocessor System-on-a-Chip (SoC) built using a mixed-technology 'chiplet' approach. An 8-core/cache complex (CCX) resides on one die, called as CCD. There are multiple dies on single SoC chip. 'I/O' die (IOD), containing the Interconnect called Scalable Data Fabric (SDF) & Scalable Control Fabric (SCF)., I am a part of the Server SoC Test Bench team. 

Responsibilities : 

1.Our team's responsibility is to handle complete SoC test bench tasks. Like soc UVM environment setup, instantiation of different kind of UVCs at multiple interfaces.

2.Implement a new test bench component e.g., soc monitor, memory models, checkers, cache Models, DPI layer implementations, soc initialization sequence implementations.

Project.5 : TRACE Block Level as well as MSS Top Level Verification

System Verilog UVM Methodology

12 months

Description :  UltraSoC's TRACE IP provides a universal on-chip monitoring, analytics and bare metal security solution for multi-core and data test SoC devices. It's a unified message based and vendor-independent platform that provides a high level of control over both hardware and software, as well as a non-intrusive means of collecting information in real-time. In a typical debug support platform, the flow of information is asymmetric. There is generally a large amount of trace data to be extracted with only a small amount of data flowing in, mostly for control, configuration and the occasional loading of programs. These characteristics have influenced UltraSoC's design IP leading to an architecture that is also asymmetric, biased towards the flow of data out of the SoC. The MSS (Microprocessor Sub System) system implements a UltraSoc trace system supporting four sub-systems 1) Core Complex (RISC-V processor) Instruction Trace of all five CPU's 2) Full AXI trace of a selectable single slave Interfaces on main AXI switch 3) Trace of AXI transactions (no-data) on Core complex to L2 cache 4) Trace of 34-fabric signals via the EIP interface, (32 data plus clock and valid signal). The system is configured so that 1) It is interfaced to via an external JTAG interface 2) An AXI communicator module is implemented allowing the firmware running on the Core complex to configure the UltraSoc system 3) A Virtual Console is implemented allowing message passing between the Core complex CPUS' and an external trace system In this project, we have verified scenarios of the trace block functionality at block level as well as the MSS (Microprocessor Sub System) Top level. In this, we have verified various data paths of trace block which are connected to the trace block to RISC-V processor. Configuration of the trace system from AXI interface as well as JTAG interface, we have also verified the full end to end trace functionality i.e. AXI write address channel trace, write data channel trace, read address channel and read data channel trace from all the AXI 64 bit buses, AXI 128 bit bus and RISC-V's instruction trace interface signals. We have also checked that configured AXI channel is trace properly or not, at Block Level Verification.

Responsibilities :

• Developed verification plan for block level verification.
• Developed functional coverage plan.
• Identified all the test scenarios.
• Developed block level UVM testbench environment.
• Integrated all the AXI, JTAG vips form Mentor Graphics.
• Developed test cases and test sequences.
• Developed trace data scoreboard for data trace functionality checking.
• Wrote functional coverage for the design wrapper.
• Analyzed functional coverage as well as code coverage.
• Debugged the issues. At MSS TOP Level Verification:
• Contributed in the development of verification plan for the top-level test scenarios of trace block.
• Contributed in the development of the testbench environment at the top level.
• Developed the test cases and the test sequences for all the data path on MSS top block.
• Re-used the block level scoreboard at MSS top level testbench.
• Contributed in the analysis of code coverage and toggle coverage.

Project.6 : PCI Express Controller IP Verification

System Verilog UVM Methodology

11 months

Description : The test bench architecture uses Cadence PureSpec VIP/BFM for functional verification of DUT. The PCIe compliance testing is performed using QEMU environment and with Purespec testcases. The verification environment is using Denali PureSpec VIP/BFM with UVM methodology. The main components of test bench are Global clock and reset, Configuration block, AXI BFM, APB Monitor, APB Data Checker, PureSpec Monitor, PCIe PureSpec BFM, Soma Files and Functional Coverage. Verification Component Details: PureSpec PCIe VIP: The PureSpec is capable of initiating transactions on PCIe interface when configured in active mode. The PureSpec BFM acts as RC or EP as described in the SOMA specification. When the DUT is configured as a Root Complex, the PureSpec device has to be configured as an endpoint device. The PureSpec endpoint would respond to all the applicable configuration and link training sequences to verify that the DUT is compliant to PCI Express protocol. Similarly when DUT is configured as an endpoint the PureSpec device has to be configured as a Root Complex. PureSpec BFM implements various queues and call backs functions which provides the required visibility and control for the test sequence. The Purespec BFM has provision to either generate PIPE interface of serial PHY interface. Here PIPE interface of PureSpec BFM is generated and connected to corresponding DUTs port signal. The PureSpec PCIe VIP is configured via SOMA parameter file. PureSpec AXI VIP: The PureSpec AXI VIP Master and Slave devices, configured as active devices, are connected to the DUT Slave and Master interface respectively. For each of the active devices, a corresponding pair of passive devices is also instantiated in the testbench environment. The PureSpec AXI VIP is configured via the SOMA parameter file. PureSpec APB VIP: PureSpec APB VIP is similar to the PureSpec AXI VIP and is compliant with the APB protocol. Two active slave agents are connected to the DUT master interface one is for APB IO and other is for APB PHY access. A passive master is enabled for each of the slave agents is also instantiated in testbench environment. The agents can be configured via SOMA files similar to the PureSpec AXI VIP., Involved in developing test cases & test sequences. Implemented PCIe TLP functional Coverage. Involved in modification/updation of scoreboard. Integrated APB VIP/BFM in the test bench environment. Debugged PCIe initiated test cases.

• PCIe IP 2nd Gen Functional Verification, System Verilog OVM Methodology, 14 Months, PCIe IP verification is the project in which we have verified the Xilinx design IP using the Mentor Graphics's VIP. This is the block level verification of Wutu FPGA used in the avionics display hardware system. The test bench acts as a root complex (RC) and DUT is acts as the end point (EP). The RC is only requester (generates requests transactions) and the EP is only completer (generates the completion of particular requests) except advance error reporting request messages. The DUT acts as the bridge between the PCIe and AXI interface. When RC transmits the memory write/read transaction to the EP, the DUT will get this transaction from PCIe interface and forward it on AXI master interface. Then AXI master fetches memory data. PCIe features used in the project are: 1. Single link serial differential interface. 2. Single Lane. 3. Capability register 2. 4. AER extended capability register. 5. Supports memory and configuration transactions.

Responsibilities : 

• 1.Involved in developing the test plan.
• Involved in developing the architecture of a Testbench.
• Developed virtual sequences for transaction layer and data link layer.
• Developed OVM register model. Developed register data scoreboard.
• Developed test cases transaction layer and data link layer.
• Developed register functional coverage.

Project.7 : Content Processing Module (CPM) Host Interface (HI)

System Verilog OVM Methodology

8 months

Description : The Host Interface (HI) provides an interface for the CPM to connect to CPM 1.8 CPP Fabric. It implements the PCIe endpoint functionality including the Type 0 configuration and the PCIe extended configuration that enable a host CPU to enumerate, configure and use the CPM services. The HI will materialize in the PCI hierarchy as an PCIe endpoint. In addition, the HI also translates Command Push Pull (CPP) commands to IOSF transactions and IOSF transactions to CPP commands. The HI primary usage is to support the Lookaside processing model initiated and controlled by IA via the IOSF primary interface. Inline processing model uses the IOSF-SB interface as a control path. The IOSF-SB is located in the HI RI block. 

Responsibilities : 

• Involved in developing test cases & test sequences.
• Involved in developing the coverage test plan for IOSF error reporting functionality.
• Involved in implementation of functional coverage of IOSF error reporting.

Project.8 : Function Safety Verification with Fault Simulation (ISO-26262 ASIL-D)

Description : Verified the functional safety features of ISO-26262 ASIL-D compliance block. Perform fault simulation for stuck @0 and stuck @1 faults. Debugged the undetected and unobserved faults to get 100% Diagnostic Coverage.

• Date of Birth: 06/04/1986
• Nationality: Indian