Sarang J Menon

Low Power Modes Verification:
Verified various Low Power Modes (LPMs) at the SoC level, ensuring correct sequence to enter and exit LPMs. Created testplan and C based tests .
Power Controller Verification
SoC DV of Power controller responsible for power transition of IPs in SoC .

A55 wrapper subsystem IP DV

Responsible for setting up UVM testbench , testplanning and coding tests - C and UVM tests.

Requirements Traceability Automation (Internship project):

Python based framework to automate Requirement Traceability report generation using JIRA CLI

RISC Processor with Hazard Detection and Mitigation implemented using Verilog HDL
A 5-stage Pipelined RISC Processor was implemented using Verilog HDL (in structural modelling style) - with Hazard Mitigation

Euclidean Distance Based sorting of Half Precision floating point data using Verilog

On a set of 32 2-D coordinates (in Floating Point Format), Euclidean Distances were calculated from the centroid and sorted.

4*2 SRAM Array Design -LTspice (Minor Project )
Implementation of SRAM in 6T configuration.