Saras Mani Mishra
Guwahati
Summary
Innovative and results-driven VLSI and digital design engineer with 5+ years of experience in RTL design, FPGA/ASIC implementation, and hardware-software co-design. Demonstrated expertise in developing high performance, energy-efficient neural network accelerators. Proven track record in academic research, project leadership, and mentoring, with multiple publications in top-tier IEEE journals and conferences. Adept at leveraging advanced EDA tools and programming languages to deliver robust, scalable solutions for next-generation computing systems
Overview
6
6
years of professional experience
Work History
Project scientist
NiNe Labs, IIT Guwahati
08.2024 - Current
- Leading the design and development of AI/ML and Post Quantum Cryptography co-processors, utilizing advanced RTL and hardware security techniques.
Teaching Assistant
Department of Electrical Engineering, IIT Guwahati
08.2019 - 07.2024
- Supported instruction and lab development for Digital VLSI, FPGA Lab, and Processor Organization & Architecture courses.
Erasmus Fellow (RTL Design Engineer)
03.2023 - 07.2023
- Developed and verified RTL modules for high-performance digital systems as part of an international research collaboration.
Education
Ph.D. - VLSI
Indian Institute of Technology
Guwahati11-2025
M.Tech - Electronics & Instrumentation Engineering
National Institute of Technology
Silchar07-2019
B.Tech - Instrumentation & Control Engineering
Haldia Institute of Technology
Haldia06-2015
Skills
- Platforms/Tools: Cadence Virtuoso, Innovus, Genus, Xilinx, QUARTUS/VIVADO, Design Vision, ICC2, OpenTimer, LaTeX, Linux
- Programming: Verilog-HDL/SystemVerilog, Python, C, TCL
- Specializations: Digital IC Design, RTL Design, SoC Design, Computer Architecture, ASIC Design, FPGA Design, Machine Learning
Timeline
Project scientist
NiNe Labs, IIT Guwahati
08.2024 - Current
Erasmus Fellow (RTL Design Engineer)
03.2023 - 07.2023
Teaching Assistant
Department of Electrical Engineering, IIT Guwahati
08.2019 - 07.2024
Ph.D. - VLSI
Indian Institute of Technology
M.Tech - Electronics & Instrumentation Engineering
National Institute of Technology
B.Tech - Instrumentation & Control Engineering
Haldia Institute of Technology
LEADERSHIP & MENTORING
- Teaching Assistant for VLSI System Design Lab (EE-514), Digital Circuit Design Lab (EE-313), and Embedded System and Computer Architecture (EE-312) at IIT Guwahati
- Mentored 4 M.Tech and 5+ B.Tech students on research and industry project
AREA OF INTEREST
- Digital IC Design
- RTL Design
- SoC Design
- Computer Architecture
- ASIC Design
KEY PROJECTS
Ph.D. Thesis: Design and Implementation of Efficient Training and Inference Engines for Spiking Neural Networks Across Multiple Domains, Ph.D. Digital Projects:, 1. Implementation of ECC data encoder module for SNN (SystemVerilog HDL), 2. Speed-optimized convolution core module for CNN (Verilog HDL), 3. Floating point Karatsuba multiplier (Verilog HDL, Cadence Genus), 4. Traffic light controller using Verilog HDL, 5. Half adder, full adder, Kogge-Stone adder on Cyclone V Intel FPGA, M.Tech: Conducted memristor device characterization for advanced instrumentation, B.Tech: Developed a pipelined 32-bit floating point multiplier
ACADEMIC ACHIEVEMENTS
Awarded Erasmus Fellowship Grant (2023), GATE Qualified (2016, 2017, 2018)
PUBLICATIONS
- Journals
- Mishra, S. M., et al. "FPGA-Based Adaptive LIF Neuron for High-Speed, Energy-Efficient Spiking Neural Network." IEEE Transactions on Circuits and Systems for Artificial Intelligence, 2025. [DOI:10.1109/TCASAI.2025.3568365]
- Mishra, S. M., et al. "Hardware Implementation of a Performance, Power, and Area Optimized Residual Spiking Neural Network with Edge-based Data Encoding." Submitted to IEEE TVLSI (Major revision)
- Mishra, S. M., et al. "Design of an SNN Based On-chip Training Network to Classify Atrial Fibrillation for Wearable Devices." (Under revision)
- Kundu, S., Patkar, S. S., Mishra, S. M., et al. "A 360-Degree Review of Testlin Machines: Concepts, Applications, Analysis, and the Future." Submitted to IEEE IoT Journal
- Conferences
- Mishra, S. M., et al. "Design and Implementation of a Low Power Area Efficient Bfloat16 based CORDIC Processor." 32nd International Conference Radioelektronika, Kosice, Slovakia, 2022. [DOI:10.1109/RADIOELEKTRONIKA545537.2022.9764911]
- Mishra, S. M., et al. "Comparison of Floating-point Representations for the Efficient Implementation of Machine Learning Algorithms." 32nd International Conference Radioelektronika, 2022. [DOI:10.1109/RADIOELEKTRONIKA545537.2022.9764927]
- Tiwari, A., Mishra, S. M., et al. "Design of a Low Power and Area Efficient Bfloat16 based Generalized Systolic Array for DNN Applications." 32nd International Conference Radioelektronika, 2022. [DOI:10.1109/RADIOELEKTRONIKA545537.2022.9764899]
- Saras Mani mishra, et al. “Temporal Data Encoding and On-Chip Training of an SNN for ECG Classification” 39th VLSID (accepted)
References
- Gaurav, Trivedi, Prof., trivedi@iitg.ac.in, +91-361-258-253, Indian Institute of Technology, Guwahati, Guwahati, Department of Electronics and Electrical Engineering
- Hanumant Singh, Shekhawat, Dr., h.s.shekhawat@iitg.ac.in, +91-361-258-3465, Indian Institute of Technology, Guwahati, Guwahati, Department of Electronics and Electrical Engineering