Summary
Overview
Work History
Education
Skills
Websites
Timeline
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SASWAT PADHY

SASWAT PADHY

Summary

A passionate ASIC engineer with exposure to working on latest tech-nodes & novel architectures looking for a suitable role in Low power Architecture/Design/Implementation

Overview

3
3
years of professional experience

Work History

Low Power Design Engineer

Qualcomm
India
11.2022 - Current
  • Working on lower tech node GPU deep pipe line architecture designs [shader, tensor processor, 3D rendering]
  • Power characterization using PTPX/Power Artist for various GPU cores for different GPU benchmarks
  • Power budgeting; driving Power convergence(Dynamic and Leakage) and optimization [RTL, floor-planning, pre/post CTS, PNR]
  • Pre/post silicon power issues debug
  • PPA & tradeoff analysis across the ASIC design cycle
  • PMIC buck limit planning for GPU sub-system rails
  • Silicon correlation for power & Vmin
  • Inrush current & IR droop tracking & mitigation
  • Low power design techniques: UPF, clock gating, power gating, DVFS, voltage islands, MV designs, level shifters, isolation cells and retention registers with hands-on experience in CLP
  • Power aware synthesis

Chip Design Integration Engineer

Samsung Semiconductor India R&D
07.2021 - 11.2022
  • Worked on camera ISP architecture & validated with various RTL sign-off [spyglass linting, Automatic formal linting(AFL), X- propagation checks, CDC, RDC]
  • low power estimation [GLS , EPS, PTPX]
  • Synthesis & STA constraint development
  • power aware synthesis & ECO bring up
  • have good understanding on ASIC design flow
  • development of UPF at SOC level

ASIC Design Trainee

Samsung Semiconductor India R&D
02.2021 - 06.2021
  • Worked with Simvision
  • Verdi tool targeting various module designs, compilation, debugging involving protocols like AXI, APB, I2C

Education

M.Tech in ECE (VLSI SYSTEMS) -

IIITB
Bangalore
06.2021

B.Tech in Electrical Engineering -

Veer Surendra Sai University of Technology
Burla, Odisha
05.2018

Intermediate -

Khallikote Jr. College
Brahmapur
05.2014

Matriculation -

D.A.V Public School
Brahmapur, Odisha
05.2012

Skills

    Tools:

    • Cadence Simvision, Genus, ICC , CLP
    • Synopsys DC/FC , Primetime, VCS

      Languages:

      • UPF, Verilog, TCL, Perl (beginner)

Websites

Timeline

Low Power Design Engineer

Qualcomm
11.2022 - Current

Chip Design Integration Engineer

Samsung Semiconductor India R&D
07.2021 - 11.2022

ASIC Design Trainee

Samsung Semiconductor India R&D
02.2021 - 06.2021

M.Tech in ECE (VLSI SYSTEMS) -

IIITB

B.Tech in Electrical Engineering -

Veer Surendra Sai University of Technology

Intermediate -

Khallikote Jr. College

Matriculation -

D.A.V Public School
SASWAT PADHY