Senior Design Verification Engineer
Arasan Chip Systems Inc
Jan 2022 - Present
Protocols known are UFS 3.0, 3p1, 4p0 and currently UFS4p1. Bus protocols AXI and AHB.
- Worked on UFS 4.0 host-side implementations, including Out-of-Order (OoO), Multi-Queue Command (MCQ), and Enhanced Host States (EHS) features.
- Designed and implemented advanced verification methodologies to detect and resolve defects in high-complexity designs, enhancing product reliability.
- Evaluated functionality, performance, and compliance of products in alignment with development standards to maintain strong quality
- Offered support and guidance to junior verification engineers for accelerated professional development.
VLSI Verification Engineer (2017 to 2022)
- Developed an enhanced verification environment, with a primary focus on the deep sleep feature in UFS 3.1
- Developed and executed comprehensive verification plans for complex ASIC designs, resulting in 98% coverage closure
- Over a three-year period, engaged in debugging and fixing testbench issues for UFS 2.1 and UFS 3.0 to ensure design functionality and improving efficiency by 15%
- In 2020, I spent six months working on DSI and CSI project verification.
- Generated and reviewed verification reports, ensuring compliance with project requirements.
