SATYA HARI KRISHNA LOYA

An enthusiastic and self-motivated physical design engineer looking for a challenge and responsible position as physical design engineer to apply my knowledge and skill with my hard work and patience and be world class in ASIC design

Tech Nodes which i worked: Planar , FD-SOI , FinFET , GAA FET

• TSMC - 16nm, 7nm, 5nm, N3P - Physical Design & Analog Layout (7nm , 5nm)
• Samsung - SF3, SF2 - Physical Design
• Intel - 7nm, 18A - Physical Design
• ST Microelectronics - 28nm - Analog Layout
• Texas Instruments - C021 70nm - Memory Layout, Std Cell layout

Few challenges faced in Physical Design:

Floorplan:

• Got an opportunity to do floorplan of 108 macros of an IP at Top level. With the flexibility that i learnt from fusion compiler tool , and certain guidelines that i received from designer , i did able to place the 108 macros.
• Took module placement , voltage area placement , ports placement , power planning , block shape, MSCTS into consideration while doing floorplan.
• Placement of ports of an interface partition was extremely difficult especially when dealing with low power block.
• Took the learning from the adjacent block , and keeping power intent and module placement of my block , did placement of 28k ports successfully and met the design

UPF Challenges:

• Got an opportunity to work with a block which as 7 power domains which are both ONO and Multi-Voltage. Meeting the power intent through out the flow was very challenging.
• Planning the power intent based on my block and adjacent block was challenging since Top-Level block was abutted design.

Placement and Congestion Challenges:

• Faced congestion issues on multiple designs where the domain crossing was high b/w two voltage areas (Dual Core IP), while bypassing the middle voltage area.
• Thanks to the advance techniques that i have used and features of fusion compiler which did help in mitigating the congestion both at compile stage and postcts opt stage.
• Congestion during hold optimization took signoff challenges to next level , where it was a learning for me to keep in mind the hold optimization of my partition and as well as adjacent partition as well.
• Choosing correct lib cells and having a knowledge of the lib cells that we are using will help understand or prevent legalization issues especially when dealing with lower nm technologies.

Clock Tree Synthesis , Latency and Skew Balancing Challenges:

• A requirement of balancing few clock ports in the design was extremely challenging. The latency of clocks to those ports must be balanced and need to see all the clocks to those ports are having same latency.
• A requirement of achieving minimum latency was top priority in the design as the block will be multiplied and maintaining the design to its best latency will have their own benefits. Successfully achieved the best latency numbers .

Signal Integrity and Router Challenges:

• SI integrity and timing closure was extremely difficult especially with lower nm technologies like SF2 , and 18A. All seems good until postcts opt will go bad during routing stage.
• Learnt to estimate SI impact on route right from compile stage based on the frequency of design , technology used and congestion present in the design.
• Thanks to few features in fusion compiler as well, which did help in mitigating the SI impact on route and thus improve the PPA and pave a way to timing closure.

DRC , LVS, ERC and EMIR:

• With experience i have in Backend Layout design (Analog , Memory and Std Cell design) , i have good handson in analyzing the shorts and opens from LVS report and fixing DRCs and mitigating EMIR.
• Had to fix 200 DRCs in one day in memory layout. And was recognized by manager after successfully fixing the DRCs manually.