Sayan Paul

• Spearheaded post-silicon validation of high-performance analog IPs including [e.g., PLLs, clock buffers], ensuring functionality across process, voltage, and temperature (PVT) corners.
• Designed and automated test benches using [Python/MATLAB/LabVIEW], reducing test cycle time.
• Collaborated closely with design teams to analyze failure signatures, debug root causes at schematic level, and provide valuable design feedback.
• Characterized [device/IP] performance metrics such as jitter, offset, PSRR, and loop stability, bridging the gap between silicon results and simulation.
• Gained hands-on understanding of analog circuit behavior including biasing, compensation, and layout-induced variations.
• Built strong foundations in analog design through [self-projects, coursework, TI internal learning modules], with focus on [e.g., op-amp design, LDO architecture, or noise analysis].

Have Designed Sub-Harmonic rejection Filter for Frequency Doubler stage with a rejection of 38dB.

Have Designed Low Voltage CML based FlipFlops for RF Operations.