sharath seshadri

Dedicated 11 years of successful experience in Analog layout designing. Full Custom Layout Analog Layout Techniques - Floorplan, placement, matching & shielding Antenna Checks and Electrical Rule Checks Physical Verification – DRC, LVS, Extraction Reliability Verifications – EM & IR Worked on technologies ranging from 250nm to 7nm Quick Understanding of design rules and verification for of CMOS Processes, SOI process and Finfet process Worked in Technologies likes TSMC 7nm, 5nm & SF 2nm process Experience in the Layout of Analog IP’s like PLL, DLL, Bandgap, LDO, DAC including physical verification checks likes DRC, LVS, Density, HVDRC etc. Experience working on the Pad ring verification. Worked on High Voltage BCD process in 180nm to 65nm CMOS with voltage up to 40V Experience in handling full IP layout from Area Estimation, Floor planning, placement, and routing until the IP Level. Knowledge of Latch-up Metal density and Antenna in all the technology nodes Experience in handling full layout from Area Estimation, Floor planning, placement, and routing until the IP Level Worked in different Multinational Companies & have Interacted with lot of overseas clients in US, France, and Taiwan Have been leading a Team of Four to 10 people from past 4 years. Developed cadence Skill based Memory tiller for different memory architectures Skill automation as per the requirement Have good communication skills and willingness to work with a global team Fast learner, Hardworking, self-motivated and ability to work in organization where I can efficiently contribute and enhance my learning, knowledge & skills to meet company goals.