Shaheen Sulthana

6+ years of Experience in Custom/Analog/RF/SERDES Layout Design. Specialized in the design and implementation of analog integrated circuits, focusing on the physical layout components and deep understanding of semiconductor physics, circuit design principles, and layout techniques to ensure optimal performance and manufacturability. Experience in layout designs for 180nm down to 2 nm process nodes.

Professional Experience:

• Expertize in efficient floor planning, area optimization, parasitic minimization and thorough understanding of design rules, device matching, sharing, various design challenges, including ESD issues, BUMP placement, IP integration.
• Expertize in debugging DRC, LVS, ANT, Density, EMIR.
• Hands-on experience on Latch up, Antenna Effect, Density, ESD, deep sub-micron effects and LLE in macro top and sub-blocks. Worked on Deep N-well Concept.
• Involved in development of high speed SerDes IPs with data-rate up to 48Gbps, including MPHYG5/G6, PCie, HPC, Ethernet, Vby1TX, RF IPs. Hands on experience on TX,RX,PLL modules.
• Built LC-VCO which was a first-pass silicon success.
• Hands -on experience on tape out process (LDFW/LEF/Cross fire).
• Collaborating with circuit designers to debug issues and ensure timely resolution. Responsible for debugging failures to the root cause ,Address issues related to parasitic capacitance and inductance to enhance circuit performance and full chip-level integration support.
• Worked with Customers to understand their flow requirements and map them to features within Custom Layout design Platform.
• Developed and maintained detailed documentation for layout processes, including design rules, methodologies, and best practices to streamline future projects.
• Participated in design reviews and provided critical feedback on layout strategies, contributing to the overall improvement of design quality and efficiency.
• Demonstrates strong analytical, communication, and teamwork skills, with proven ability to quickly adapt to new environments and results-oriented mindset. Eager to contribute to team success and further develop professional skills. Brings positive attitude and commitment to continuous learning and growth.
• Proven ability to handle multiple tasks effectively and efficiently in fast-paced environments. Recognized for taking proactive approach to identifying and addressing issues, with focus on optimizing processes and supporting team objectives.

Leadership:

• Managed layout team of 8 people
• Built a new 4 member TECH COMMITTEE @SAMSUNG.
• Co-lead/Team member- QA Layout
• Hiring, Mentorship and training for Layout.
• Active participation in Internal and External paper and tutorial/poster.
• Attended Conference(Cadence/SNUG/SIEMENS/IEEE)

Circuit Simulation:

• Inductor/TCOIL design and EMX simulation
• PEX generation

My biggest achievement includes successfully designing and delivering a high-speed SERDES interface for a high-performance networking chip and LCVCO, which resulted in a significant increase in data transmission rate . My attention to detail and strong problem-solving skills have been instrumental in ensuring the manufacturability and reliability of my designs to reduce TAT which lead to project success.

SPOT AWARD: Samsung semiconductor India R and D, Jan 2025:

Extra mile: Layout design optimization to meet the quality and smooth delivery MPHY TX IP

Recognition: ThankQ: Qualcomm Technologies ,Sep 2023

On time delivery with high quality RFFE next generation monolithic FEM test chip

Hands-on Experience on High-Speed Blocks:

⦁ MPHYG5/G6, PCieGen-3, Vby1TX,HSSTP IPs

⦁TX: Serialiser, Driver, CD and TCOIL

⦁PLL: VCO, INDUCTOR, PFD, CP and LPF

⦁RX: PI, CDR, CTLE

⦁RF : LNA,PA blocks

⦁Bandgap/LDO

IBIS-AMI generation Through System Vue- KEYSIGHT TECHNOLOGIES -Jan 2025

Cadence Layout Technology -Cadence Virtuoso -Apr 2023