SHAIK JANI

• Collaborated with cross-functional teams to ensure alignment on design specifications and requirements.
• Implemented innovative techniques for floorplanning and timing closure, enhancing design efficiency.
• Conducted DRC/LVS sign-off processes, ensuring compliance with industry standards and specifications.
• Streamlined design review processes, improving turnaround times for project approvals and revisions.
• Led initiatives in process automation that reduced manual tasks within physical design workflows.
• Provided valuable feedback during design reviews, contributing to ongoing improvements in product quality and performance.
• Analyzed and resolved complex design issues, driving continuous improvement initiatives within team workflows.
• Resolved complex physical design issues promptly, minimizing delays in project timelines while maintaining high standards of workmanship.
• Identified and resolved critical issues in layout routing, significantly improving overall design robustness.

Project: 2

Tools : FusionCompiler,Caliber Technology Node: 5nm

Design Statistics :15Metal Layers, 75Macros, 2.27M+ cell count ,2GHz Frequency, 8 Clocks

Responsibilities:

· I am working on initial Netlist (Project is in the beginning stage) .As of now block is converging well.

· One block having multi voltage domain and Block shape is rectilinear,which are having 75 macros . and another blcok is channel partition which is having low complexity

· Faced issues at the time of macro placement and voltage area sizes. There are 8 voltage domains in these two blocks exclude default voltage domain.I faced over utilization issues in voltage areas. Tried so many floorplans and voltage area shapes to get the best results. And applied density screens and partial blockages

· Applied partial blockages to free the congestion where more notch area and io placement.

· Main challenge faced in Timing closure and congestion reduction.

· Responsible to fix Instance Peak and Avg violations in RV stage by spreading the cells, creating power mesh for the cells and downsizing

· Fixed block level lvs,antenna,rv and drc’s violations with minimal super vison

Project: 1

Tools: IC Compiler 2 & ICV

Node: 10nm (Client : INTEL)

DesignStatistics:14 Metal Layers, 116 Macros ,579.2K Instances, 0.980GHz Frequency, 4 Clocks

Responsibilities:

· Performing Floorplan,PNR and LV for 1 block.

· Tried somany floorplans to get the best results.And applied density screens and partial blockages

· Applied partial blockages to free the congestion where more notch area and io placement.

· Fixed block level lvs,antenna and drc’s violations with minimal super vison

· Responsible to fix Instance Peak and Avg violations in RV stage by spreading the cells, creating power mesh for the cells and downsizing

Physical Verification Engineer

Roles and Responsibilities:

• Responsible for signoff physical verification for Intel chips on congested and critical blocks.
• It includes 0P8 and 0P1 reviews which includes floorplan, power plan, placement, cts and routing are meeting the signoff quality or not.
• Checking results and sending feedback and fixes document to SD team.
• It Includes Base DRC clean, Metal DRC, debugging and fixing LVS, Antenna, ERC, Density Checks, RV fixes and ECO Roll up.
• fixing manual DRC, LVS, DENSITY, Latch-up, ANTENNA fixes, RV fixes, IR drop, congested rerouting, shielding & manual ECO implementation in block level.

Tools used: FC, ICCII, ICV, ICWB ,Calibre

Technology: INTEL - 22 nm, 10 nm, 7 nm, and 5 nm.