Shalini Vallabhaneni
Staff Engineer
Bangalore
Summary
Passionate and focused VLSI Engineer with experience of 6 years in Standard Cell Layout and Validation seeking a challenging opportunity to exhibit skill, grow expertise and drive organizational success. Adept at learning new tools and skills.
Overview
6
6
years of professional experience
6
6
years of post-secondary education
Work History
Staff Engineer
Synopsys India Pvt. Ltd.
2 2020 - Current
- Led team in development and delivery of standard cell packages for different tech nodes by ensuring all packages met high standards of quality and performance
- Collaborated with cross teams to align with customer requirements to meet goals
- Worked closely on Apache Power view generation and validation, assisted in debugging various issues
- Worked as part of methodology team to enhance flow, improve efficiency, and reduce turn-around time
- Independently developed automated workflows to increase efficiency and reduced discrepancies
- Designed 1001 Ring Oscillator Custom layout in 6T,7.5T and 9T.
A&MS Layout Engineer - I
Whizchip Technologies Pvt. Ltd, INVECAS Technologies Pvt. Ltd
07.2018 - 01.2020
- During employment period at Invecas, have worked on following projects
- Designed standard cell layouts from scratch, floor plan to top level routing, perform PV checks DRC,LVS,ANT and EM
- Review/discussion on floor-plan and completed layouts with team lead and teammates for delivering quality layout.
Education
B.Tech in Electronics & Communication Engineering -
ANURAG ENGINEERING COLLEGE
KODAD 08.2011 - 05.2015
M.Tech in VLSI Design Stream -
ANURAG ENGINEERING COLLEGE
KODAD 09.2015 - 09.2017
ANURAG ENGINEERING COLLEGE
KODADSkills
Tech nodes: 2nm, 3nm, 4nm, 5nm, 7nm, 8nm, 12nm, 22nm, 28 nm, 40nm
Platform: Linux, Windows
Tools: Virtuoso L & XL, Custom_Compiler, Siliconsmart, Hspice, Redhawk, Library compiler, ICCII Compiler
Languages: Shell Scripting, Perl, Tcl, Basics of Python
Languages
English
Bilingual or Proficient (C2)
Telugu
Bilingual or Proficient (C2)
Hindi
Intermediate (B1)
Timeline
A&MS Layout Engineer - I
Whizchip Technologies Pvt. Ltd, INVECAS Technologies Pvt. Ltd
07.2018 - 01.2020
M.Tech in VLSI Design Stream -
ANURAG ENGINEERING COLLEGE
09.2015 - 09.2017
B.Tech in Electronics & Communication Engineering -
ANURAG ENGINEERING COLLEGE
08.2011 - 05.2015
Staff Engineer
Synopsys India Pvt. Ltd.
2 2020 - Current
ANURAG ENGINEERING COLLEGE
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