Sharanya Khamithkar
SoC Design Engineer
Hyderabad
Summary
Creative and innovative prospect determined to bring ideas to life through cutting-edge technology and design techniques. Team player with strong problem-solving skills to contribute effectively to projects and teams. Considers unique and unconventional solutions to deliver exceptional results.
Overview
6
6
years of professional experience
2
2
years of post-secondary education
Work History
SoC Design Engineer
Intel
Hyderabad
10.2022 - Current
- Ongoing – LEC lead for Client project. Debugged multiple issues and given feedback/fixes to PnR. Reviewing and running Audit checks for 15 partitions
- FEV execution for CPU core project, Carried out FEV Audit and paranoia checks.
- Carried out Formality based FEV in a test chip to ease the FEV convergence.
- Submitted a paper “Achieving Faster Turn-Around-Time for Formal Equivalence Verification of PPA centric Multimillion Gates Designs” at Synopsys’s SNUG 2022.
- Developed Feature extraction Perl script, which is the input for AI Model, for predicting Aborts before even comparison in Conformal.
- Contributed to Intel DTTC paper “Machine Learning based FEV Abort Prediction for High-Quality Design Hand-off”.
- Supported team with Flow issues and given Training/Demo on FEV flow in new Env.
- Mentored Interns to work smart/to ramp up w.r.t. FEV flow and Conformal debug.
Automation Design Engineer
Intel
Bangalore
10.2018 - 09.2022
- Own and deliver best-in-class design automation FEV flow for all product groups at Intel globally.
- Responsible for providing support for all product groups at Intel India.
- Enabled and pioneered FEV Abort prediction ML App.
- Re architecture of FEV Flow to align to the overall Intel's cheetah environment guidelines and meet Customer requirements.
- Responsible for Regression/Code coverage FEV runs to catch/correct the enhancements/bugs in the flow before release.
- Worked with multi-site teams to pioneer new tool for Regressions and Code coverage.
- Hands on experience with Perforce and Tools installations.
- Developed multiple Automation scripts to make Designer's life easy.
Jr Engineer
Altran Technologies
Bangalore
06.2017 - 10.2018
- Responsible for 6 less complex partitions to take from RTL to GDS.
- Worked on automation for DRC fixes in Physical Verification.
- Performed and consolidate the quality/health checks for 40+ blocks.
- Came up with an automation which consolidate the Quality checks reports at full chip level for ease of analysis.
- Recognition from Intel stakeholders for multiple Automation scripts for reducing manual effort.
Education
Post Graduation - VLSI System Design
M S Rmaiah University of Applied Sciences
Bangalore 01.2014 - 01.2016
Skills
Computer-Aided Design (CAD)
Accomplishments
- Intel DTTC paper “Machine Learning based FEV Abort Prediction for High-Quality Design Hand-off”.
- Technical paper “Achieving Faster Turn-Around-Time for Formal Equivalence Verification of PPA centric Multimillion Gates Designs” at Synopsys’s SNUG event 2022.
- Multiple Division Recognition awards at Intel.
- Self-motivated individual with good technical problem solving and debugging skills.
Hobbies
- Love to travel and enjoy nature
- Photography
Timeline
SoC Design Engineer
Intel
10.2022 - Current
Automation Design Engineer
Intel
10.2018 - 09.2022
Jr Engineer
Altran Technologies
06.2017 - 10.2018
Post Graduation - VLSI System Design
M S Rmaiah University of Applied Sciences
01.2014 - 01.2016
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