SHASHANK H TELI

Driven by a passion for technological innovation and community service, I excelled at NITK Surathkal, designing advanced digital multipliers and a 16-bit ALU, showcasing my proficiency in VHDL, Verilog, and Python. My collaborative skills shone as a ROTRAT club member, leading impactful social welfare initiatives.

• Design and Validation of RISC-V Single Cycle Processor: Developed a RISC-V single-cycle processor with modular and scalable architecture, executing each instruction within a single clock cycle for optimized efficiency. Achieved rigorous validation and reliability checks, utilizing vivado to ensure precise functionality in alignment with RISC principles.
• Advanced 16-bit ALU Implementation and Validation: Developed a high-precision 16-bit Arithmetic Logic Unit (ALU) capable of various arithmetic and logical operations, validated against a Python script for accuracy. Integrated overflow and underflow detection, error correction, and configurable modes. Optimized performance through pipelining, parallel processing, and power-saving techniques. Explored scalability for future integration with CPU designs.
• Design and Evaluation of Advanced Multipliers Using Verilog in Vivado:This project implements various multipliers using Verilog in Vivado, including array, sequential, and advanced Booth multipliers (radix-2 and radix-4). Each multiplier is designed, simulated, and tested to assess performance. The analysis highlights trade-offs and helps identify the most efficient multiplication method for digital systems.

As a member of the ROTRAT club, I actively participated in organizing events and collaborating with NGOs for social welfare initiatives. Our efforts focused on event management and community service, aiming to make a positive impact on society. We combined our organizational skills with a passion for social change to create meaningful experiences and contribute to the betterment of our community.

Summer Internship, NITK Surathkal, Department of ECE, Conducted research under Professor Ramesh Kini on designing and evaluating advanced digital multipliers and a 16-bit ALU. Implemented various multiplier designs, including array, sequential, and Radix-2 and Radix-4 Booth multipliers, and developed a 16-bit ALU for diverse operations. Achieved comprehensive performance analysis and rigorous validation through Python-based output comparisons, enhancing understanding of multiplier techniques and ALU functionalities.