SHASHANK S

Motivated engineering professional with experience as a Graduate Engineer Trainee - Physical Design Engineer. Proficient in using Cadence tools for physical design and circuit optimization. Seeking a challenging Physical Design Engineer role to leverage skills, contribute to innovative projects, collaborate with a dynamic team, and continuously learn and upskill in cutting-edge semiconductor design solutions within a forward-thinking organization.

DTMF

• Implemented a DTMF Receiver using Cadence Innovus, covering full Physical design flow. Managed a large-scale design with 985 modules, 5906 standard cells, 71 pads, and 4 macros. Executed floorplanning, power planning, placement. Optimized cell utilization, incorporating 266 combinational, 178 sequential, and 18 tristate cells. Integrated specialized components including buffers, inverters, and delay cells. Demonstrated expertise in handling complex digital design and advanced EDA tools.

ASIC ENTITY

• Integrated 3,105 modules, demonstrating proficiency in large-scale circuit design Incorporated 17,886 standard cells, 313 pad instances, 29 macros showcasing expertise in digital logic implementation. Optimized cell utilization, incorporating 317 combinational, 150 sequential, and 10 tristate cells. Successfully completed critical initial stages including floorplanning and power planning. Currently optimizing placement stage to enhance performance, minimize area, and improve overall design efficiency.

• Fitness
• Travelling