Shashidhara M

Researcher with a Ph.D. in Spintronics and expertise in Spin-Orbit Torque Magnetic Tunnel Junctions (SOT-MTJs), 2D materials, and micromagnetic modeling. Proven track record of publishing in high-impact journals (e.g., IEEE Transactions ) and pioneering advancements in Logic-in-Memory (LiM) architectures for non-volatile computing. Seeking a postdoctoral position to further contribute to cutting-edge research in low-power memory and computing technologies.

1. Shashidhara M, S. Srivatsava, S. Panwar, V. Nehra, R. Kamal and A. Acharya, ”Impact of Unconventional Torque on the Performance ofWeyl-Semimetal-Based SOT-MTJ: A Micromagnetic Study,” in IEEE Transactions on Electron Devices, vol. 71, no. 3, pp. 2177-2183, March 2024, doi: 10.1109/TED.2024.3353707

2. Shashidhara M., V. Nehra, S. Srivatsava, S. Panwar and A. Acharya, ”Investigation of Field-Free Switching of 2-D Material-Based Spin–Orbit Torque Magnetic Tunnel Junction,” in IEEE Transactions on Electron Devices, vol. 70, no. 3, pp. 1430-1435, March 2023, doi: 10.1109/TED.2023.3237654.

3. Shashidhara M., S. Srivatsava, S. Panwar and A. Acharya, ”Spin-Orbit Torque Magnetic Tunnel Junction based on 2-D Materials:Impact of Bias-Layer on Device Performance,” in Solid-State Electronics, 2023 Volume 208, 2023, https://doi.org/10.1016/j.sse.2023.108757.

4. S. Srivastava, S. Panwar, Shashidhara. M., L. Chandra, N. Mishra and A. Acharya, “Influences of Source/Drain Extension Region on Thermal Behavior of StackedNanosheet FET,“ in IEEE Transactions on Electron Devices, vol. 71, no. 3, pp. 2171-2176, March 2024, doi: 10.1109/TED.2024.3351596.

5. S. Srivastava, Shashidhara M. and A. Acharya, ”Investigation of Self-Heating Effect in Tree-FETs by Interbridging Stacked Nanosheets: A Reliability Perspective,” in IEEE Transactions on Device and Materials Reliability, Dec 2022, doi: 10.1109/TDMR.2022.3227942.

6. S. Panwar, S. Srivastava, M. Shashidhara and A. Acharya, ”Performance Evaluation of High-K Dielectric Ferro-Spacer Engineered Si/SiGe Hetero-Junction Line TFETs: A TCAD Approach,” in IEEE Transactions on Dielectrics and Electrical Insulation, vol. 30, no. 3, pp.1066-1071, June 2023, doi: 10.1109/TDEI.2023.3266413.

Best Student Research Forum Award, 38th International Conference on VLSI Design (VLSID), 2025.

Received 1200 USD grant from Texas Instruments and DST, India for UG projects.

Qualified in GATE 2019 and GATE 2017 (All India Entrance Test).

RISC-V Based SoC Design: 5-day internship using Google SkyWater PDK.

Physical Design Training: 6-month training on ICC2 Compiler at VLSiGuru Ltd, Bangalore.

Certified Courses:
"Real-Time Embedded Systems" (Cranes Software, Bangalore).
"ASIC Front-End Design" (M.S. Ramaiah Advanced Studies, Bangalore).

I hereby declare that all the above-mentioned details are true to the best of my knowledge.

Shashidhar M