Amiya V M
Design Verification Engineer
Bengaluru
Summary
Trained Design Verification Engineer with a strong background in SV and UVM. Currently employed at AIonSi, working for client Meta as a Design Verification Engineer, focusing on testing and debugging verification tests. Actively seeking a position where I can contribute as a Design Verification Engineer and continue to grow in the field of design verification.
Overview
1
1
year of professional experience
Work History
Design Verification Engineer
AIonSi India Pvt Ltd
07.2024 - Current
- Currently working for Meta as Verification Engineer ,supporting the debugging of regression failure in a NOC subsystem.
- Worked on D_MEM_SC IP Verification:
Developed SV and UVM testbench from scratch.
Developed monitor and scoreboard for checking the
datapath.
Developed functional coverage analysis.
- Worked on APB and AXI protocols.
Tools: Synopsys VCS, Verdi.
Technology: SV, UVM.
Education
Advanced VLSI Design And Verification Course -
Maven Silicon VLSI Training Centre
Bengaluru, India 04.2001 -
Master of Technology - VLSI And Embedded Systems
Govt. Model Engineering College
Kerala 04.2001 -
Bachelor of Technology - Electronics And Communications Engineering
Adi Shankara Institute of Engineering
Kerala 04.2001 -
Skills
HDL: Verilog
HVL: System Verilog
TB Methodology: UVM
Protocols: AXI, APB, USB3
EDA Tool:
Synopsys – VCS
Mentor Graphics – Questasim
Xilinix - ISE
Timeline
Design Verification Engineer
AIonSi India Pvt Ltd
07.2024 - Current
Advanced VLSI Design And Verification Course -
Maven Silicon VLSI Training Centre
04.2001 -
Master of Technology - VLSI And Embedded Systems
Govt. Model Engineering College
04.2001 -
Bachelor of Technology - Electronics And Communications Engineering
Adi Shankara Institute of Engineering
04.2001 -
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